Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
ade06f3780
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
89a30e7e37
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
09dcb56217
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
6da7849d27
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
Ross Thompson
c50a2bd8bf
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
d15cf5c65c
Added comments about why it is not possible to use FlushWay and VictimWay directly.
2022-12-09 17:07:35 -06:00
Ross Thompson
38adcb5b17
Minor simplification of cacheway way selection muxes.
2022-12-09 16:42:05 -06:00
Ross Thompson
9806babe9e
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
0fdbfb87eb
Removed commented code.
2022-12-05 17:21:56 -06:00
Ross Thompson
bcb927d172
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
2022-12-05 17:19:51 -06:00
Ross Thompson
2bcaacb179
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
b84b709182
Optimized way selection logic.
2022-12-04 12:30:56 -06:00
Ross Thompson
74d5ccc2b1
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
2022-12-04 01:20:51 -06:00
Ross Thompson
62e495c739
Moved selectedway mux into cacheway. It makes way more sense there.
2022-12-04 01:15:47 -06:00
Ross Thompson
e1ac736d43
Rename LineByteMux to FetchbufferbyteSel.
2022-12-04 01:00:04 -06:00
Ross Thompson
1d9b5badee
Properly flush cacheLRU.
2022-12-01 17:32:58 -06:00
Ross Thompson
cb310bfb1d
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
Ross Thompson
813b2963fb
More optimization.
2022-11-30 11:26:48 -06:00
Ross Thompson
da7b13ba0a
Removed reset on dirty cache bits.
2022-11-30 11:04:37 -06:00
Ross Thompson
5e5cca6ae1
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
ac3e02692b
Preparing to merge dirty and tag srams.
2022-11-30 10:40:48 -06:00
Ross Thompson
8692ccbafb
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
Ross Thompson
e3577781b0
Optimization of cacheway.
2022-11-29 18:30:47 -06:00
Ross Thompson
9e4166407b
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
2022-11-29 14:51:09 -06:00
Ross Thompson
179d321683
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
1736983557
Cleanup cacheLRU.
2022-11-22 14:59:01 -06:00
Ross Thompson
2ae7b555be
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
84679c0062
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
a1f39a8186
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
9b2236b2a0
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
5f7b0b8a9b
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
Ross Thompson
900a326a23
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
Ross Thompson
f03d5d3ac8
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
31d5eabd77
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
98d4929c57
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
f9a04c13df
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
e5cae3bfa0
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
92d7be645b
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
52e8e0f5ef
Modified cache lru to not have the delayed write.
2022-10-04 15:14:58 -05:00
Ross Thompson
afc6934249
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
dfe6bdd06d
Found a hidden bug in the cache to bus fsm interlock.
2022-09-26 17:41:30 -05:00
