David Harris
08e494dd7d
HPTW: factored out PageTableENtry
2021-07-17 04:40:01 -04:00
David Harris
bd270acdb6
more cleaning up FSM
2021-07-17 04:35:51 -04:00
David Harris
6d8a6eeba0
cleaning up FSM
2021-07-17 04:26:41 -04:00
David Harris
330e500442
Simplify FSM
2021-07-17 04:12:31 -04:00
David Harris
03ef3f7f17
Pulled TranslationPAdr mux out of HPTW FSM
2021-07-17 04:06:26 -04:00
David Harris
5698433463
Simplified bad PTE detection
2021-07-17 03:30:17 -04:00
David Harris
ac67342dd4
Pulled out shared PTEReg
2021-07-17 03:21:09 -04:00
David Harris
86ca9abe42
Flip-flop clean-up
2021-07-17 03:15:47 -04:00
David Harris
9a15a2f7df
Flip-flop clean-up
2021-07-17 03:12:24 -04:00
David Harris
8241dd4599
Flip-flop clean-up
2021-07-17 03:10:17 -04:00
David Harris
a8a5fa4b3c
Started pagetablewalker cleanup: combined state flops shared for both RV versions
2021-07-17 02:53:52 -04:00
David Harris
b65788d165
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
Ross Thompson
46bce70e42
Fixed walker fault interaction with dcache.
2021-07-16 12:22:13 -05:00
Ross Thompson
e0f719d513
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
2021-07-16 11:12:57 -05:00
Kip Macsai-Goren
abd5b1c02d
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
2021-07-15 18:30:29 -04:00
Ross Thompson
e5d624c1fa
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
b9902b0560
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
2021-07-15 11:00:42 -05:00
Ross Thompson
ba1e1ec231
Finally have the ptw correctly walking through the dcache to update the itlb.
...
Still not working fully.
2021-07-14 22:26:07 -05:00
Ross Thompson
3e57c899a2
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
David Harris
861ef5e1cb
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
2021-07-13 09:32:02 -04:00
David Harris
d3ab6b192a
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
David Harris
5c2f774c35
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
74b6d13195
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
Ross Thompson
94c3fde724
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
2021-07-08 18:03:52 -05:00
David Harris
4f1a85ca7c
Eliminate reserved bits from TLB RAM
2021-07-08 17:35:00 -04:00
David Harris
38772de21f
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
2021-07-08 16:58:11 -04:00
David Harris
1190729896
TLB cleanup to match diagrams
2021-07-08 16:52:06 -04:00
David Harris
5d5274ec73
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-07 06:32:29 -04:00
David Harris
2bab3f769b
Renamed tlb ReadLines to Matches
2021-07-07 06:32:26 -04:00
Abe
b757c96b2d
Changed SvMode to SVMode on line 76
2021-07-06 23:28:58 -04:00
David Harris
af619dcd75
Added ASID matching for CAM
2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
8350622f65
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd
more TLB name touchups
2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
e08a578908
fixed upper bits page fault signal
2021-07-06 18:32:47 -04:00
David Harris
2e2aa2a972
connected signals in tlb by name instead of .*
2021-07-06 17:22:10 -04:00
David Harris
ee3a321002
changed tlbphysicalpagemask to structural
2021-07-06 17:16:58 -04:00
David Harris
f960561cbb
changed tlbphysicalpagemask to structural
2021-07-06 17:08:04 -04:00
David Harris
032c38b7e7
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
Ross Thompson
3345ed7ff4
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
David Harris
30fdd7abc8
Cleaned up tlb output muxing
2021-07-06 10:44:05 -04:00
David Harris
d58cad89a8
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
2021-07-06 10:38:30 -04:00
David Harris
694badcc6b
Created tlbcontrol module to hide details
2021-07-06 03:25:11 -04:00
David Harris
8b23162d6d
Fixed adrdecs to use Access signals for TIMs
2021-07-05 23:42:58 -04:00
David Harris
71711c54c9
Don't generate HPTW when MEM_VIRTMEM=0
2021-07-05 23:35:44 -04:00
David Harris
179c8d3ed4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-05 23:23:17 -04:00
David Harris
6bac566bb7
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
2021-07-05 20:35:31 -04:00
Ross Thompson
530ddd667b
Fixed combo loop in the page table walker.
2021-07-05 16:37:26 -05:00
Ross Thompson
2a62ee2e70
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-05 16:07:27 -05:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
07f2064c19
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
Ross Thompson
b2c5c3f637
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 17:07:57 -05:00
David Harris
b0f199b574
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
2021-07-04 18:05:22 -04:00
Ross Thompson
02721c29dc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:54:31 -05:00
David Harris
8b707f7703
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:53:08 -04:00
David Harris
80666f0a71
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
Ross Thompson
a252416535
Removed the TranslationVAdrQ as it is not necessary.
2021-07-04 16:49:34 -05:00
Ross Thompson
7f62808544
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
David Harris
07ef67e537
Restructured TLB Read as AND-OR operation with one-hot match/read line
2021-07-04 17:01:22 -04:00
David Harris
8337d6df68
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
2021-07-04 16:33:13 -04:00
David Harris
c281539f36
TLB cleanup
2021-07-04 14:59:04 -04:00
David Harris
81742ef9e2
TLB cleanup
2021-07-04 14:37:53 -04:00
David Harris
152923e552
TLB minor organization
2021-07-04 14:30:56 -04:00
David Harris
7e22ae973e
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
1b39481a16
TLB mux and swizzling cleanup
2021-07-04 12:53:52 -04:00
David Harris
735f3b4217
Replaced generates with arrays in TLB
2021-07-04 12:32:27 -04:00
David Harris
67e191c6f3
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
ccd9c05303
Switched to array notation for pmpchecker
2021-07-04 10:51:56 -04:00
David Harris
9645b023c9
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Ross Thompson
9f16d08d0d
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
David Harris
1fa4abf7b6
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
David Harris
d44916dacf
Cleaned up PMA/PMP checker unused code
2021-07-03 02:25:31 -04:00
Ross Thompson
cf688bd3f6
Fixed up the physical address generation for 64 bit page table walker.
2021-07-02 15:49:32 -05:00
Ross Thompson
8e3149517a
Fixed up the bit widths on the page table walker for rv32.
2021-07-02 15:45:05 -05:00
Ross Thompson
7b3716c281
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
David Harris
c85e0df1ff
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
118dfa9cec
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
61027f650c
OMG. It's working!
2021-07-01 17:37:53 -05:00
Ross Thompson
6916784354
Fixed tab space issue.
2021-07-01 17:17:53 -05:00
Ross Thompson
2dc349ea6f
Fixed the wrong virtual address write into the dtlb.
2021-07-01 16:55:16 -05:00
Ross Thompson
88a18496cf
Got some stores working in virtual memory.
2021-07-01 12:49:09 -05:00
Ross Thompson
002c32d2ad
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
Kip Macsai-Goren
ac597d78c8
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Ross Thompson
c02141697d
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
David Harris
a514554eeb
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
Kip Macsai-Goren
7e06a3c04d
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
2c41da0275
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
3e19eba20d
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
David Harris
5d6dc82db2
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
1ec90a5e1f
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
de221ff2d0
Changed physical addresses to PA_BITS in size in MMU and TLB
2021-06-18 09:11:31 -04:00
