David Harris 7d857cf4bd more TLB name touchups		2021-07-06 18:39:30 -04:00
..
adrdec.sv	Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.	2021-06-24 19:59:29 -04:00
adrdecs.sv	Fixed adrdecs to use Access signals for TIMs	2021-07-05 23:42:58 -04:00
decoder.sv	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
mmu.sv	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
pagetablewalker.sv	Don't generate HPTW when MEM_VIRTMEM=0	2021-07-05 23:35:44 -04:00
pmachecker.sv	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
pmpadrdec.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
pmpchecker.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
tlb.sv	more TLB name touchups	2021-07-06 18:39:30 -04:00
tlbcam.sv	more TLB name touchups	2021-07-06 18:39:30 -04:00
tlbcamline.sv	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
tlbcontrol.sv	more TLB name touchups	2021-07-06 18:39:30 -04:00
tlblru.sv	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
tlbphysicalpagemask.sv	connected signals in tlb by name instead of .*	2021-07-06 17:22:10 -04:00
tlbpriority.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
tlbram.sv	Created tlbcontrol module to hide details	2021-07-06 03:25:11 -04:00
tlbramline.sv	Fixed TLB_ENTRIES merge conflict and handling of global PTEs	2021-07-04 18:05:22 -04:00