kipmacsaigoren
cc4ad218cb
added new fun ways of putting inputs into the priority thermometer
2021-09-17 12:00:38 -05:00
kipmacsaigoren
97c474327c
changed priority circuits for synthesis and light cleanup
2021-09-15 12:24:24 -05:00
David Harris
12bd351edf
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
James E. Stine
02a1fda650
Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR
2021-09-03 10:26:38 -05:00
Ross Thompson
35e57a7c61
partial dcache reorg.
2021-08-25 12:42:05 -05:00
Ross Thompson
a70d51f4c9
Modified the hptw's simulation error message so that synthesis does not attempt to include this statement.
2021-08-16 10:02:29 -05:00
Ross Thompson
ef55b30e99
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-26 11:55:00 -05:00
Ross Thompson
60177b92a6
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
kipmacsaigoren
f3579032bd
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
David Harris
5d2b30e332
Removed LEVELx states from HPTW
2021-07-23 08:11:15 -04:00
Ross Thompson
dac93bb366
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
c69a5dc8a6
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
71375ba655
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:39:07 -05:00
Ross Thompson
313bc5255c
Improved address bus names and usages in the walker, dcache, and tlbs.
...
Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Kip Macsai-Goren
4eaf95de60
Fixed TLB parameterization and valid bit flop to correctly do instr page faults
2021-07-21 14:44:43 -04:00
Kip Macsai-Goren
2614df627e
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
4d53b9002f
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
4f8f52f283
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
David Harris
8317be5aed
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
3f7a3b280e
HPTW: Simpliifieid PRegEn
2021-07-18 03:35:38 -04:00
David Harris
60bd27a40e
Removed EndWalk signal and simplified TLBMissReg
2021-07-18 03:26:43 -04:00
David Harris
d9750c16a5
Pushing HPTWPAdrM flop into LSUArb
2021-07-17 19:39:18 -04:00
David Harris
586341a41a
Simplified VPN case statement
2021-07-17 19:34:01 -04:00
David Harris
35b7577be2
Finished HPTW TranslationPAdr simlification
2021-07-17 19:27:24 -04:00
David Harris
2b1fdfbae2
Further TranslationVAdr simplification
2021-07-17 19:24:37 -04:00
David Harris
b785a20f90
Continued Translation Address Cleanup of TranslationPAdrMux
2021-07-17 19:16:56 -04:00
David Harris
fc88b3a693
Continued Translation Address Cleanup
2021-07-17 19:09:13 -04:00
David Harris
6536ef8dce
Refining address interface between HPTW and LSU
2021-07-17 19:02:18 -04:00
David Harris
7b92e7e590
Fixed bad register in I-FSD-01 Imperas test.
2021-07-17 17:08:07 -04:00
David Harris
af5e1f7f39
Finished removing PageTableEntry redundant signals from hptw
2021-07-17 15:50:52 -04:00
David Harris
d4eeabe355
hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE
2021-07-17 14:48:44 -04:00
David Harris
86e04c080d
hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states
2021-07-17 14:36:27 -04:00
David Harris
714eef4a1a
hptw: Eliminated A and D bit faults while walking page table, per spec
2021-07-17 14:29:20 -04:00
David Harris
90c5312f85
hptw: Simplified TranslationVAdr calculation based just on DTLBWalk
2021-07-17 14:16:33 -04:00
David Harris
42aee1db30
hptw: renamed DTLBMissQ to DTLBWalk
2021-07-17 14:13:00 -04:00
David Harris
6f22e9a393
hptw: renamed ADRE to ADR
2021-07-17 14:02:59 -04:00
David Harris
3ce22a60b3
hptw: replaced PreviousWalkerState with a PageType FSM
2021-07-17 13:54:58 -04:00
David Harris
89fd653cc1
hptw: removed ITLBMissFQ
2021-07-17 13:44:08 -04:00
David Harris
87aa527de7
hptw: minor cleanup
2021-07-17 13:40:12 -04:00
David Harris
ea2aa469a1
hptw: Simplifed out AnyTLBMiss
2021-07-17 12:07:51 -04:00
David Harris
784e6cf538
hptw: Renamed Memstore to MemWrite
2021-07-17 12:01:43 -04:00
David Harris
0a6622a6fb
hptw: Merged RV32/64 FSMs
2021-07-17 11:55:24 -04:00
David Harris
cf0975c937
hptw: FSM simplification
2021-07-17 11:41:43 -04:00
David Harris
4469b5a4b3
hptw: default state should be unreachable
2021-07-17 11:33:16 -04:00
David Harris
9cee6c2281
hptw: factored Misaligned
2021-07-17 11:31:16 -04:00
David Harris
fa12727bbb
hptw: factored HPTWRead
2021-07-17 11:25:59 -04:00
David Harris
708f8cc3a2
hptw: factored HPTWRead
2021-07-17 11:25:52 -04:00
David Harris
ef63e1ab52
hptw: factored pregen
2021-07-17 11:11:10 -04:00
David Harris
880aa1c03a
HPTW: more cleanup
2021-07-17 04:55:01 -04:00
David Harris
a0f6c9aec1
HPTW: factored out DTLBWrite/ITLBWrite
2021-07-17 04:44:23 -04:00
