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584 Commits

Author SHA1 Message Date
David Harris
570f24a9e4 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
c92d41a597 checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
bc6332a780 fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
17e776f853 checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
bbracker
0c7681b942 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
David Harris
d7f0abca5a Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
dda035891a PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
60573b92b2 Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
David Harris
360930fe8b Fixed exe2memfile parsing of weird line in arch64d test 2021-10-30 07:26:18 -07:00
David Harris
247f247ad3 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
7df4b0c8e7 commented out some failing FPU tests 2021-10-27 11:27:34 -07:00
David Harris
582c2bf37b Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
David Harris
5783e47e1a Changes for floating point sims 2021-10-27 10:37:35 -07:00
David Harris
90cf37b881 commented out nonworking tests 2021-10-26 08:56:49 -07:00
David Harris
67adc1d7d5 removed referenc outputs 2021-10-26 08:51:49 -07:00
bbracker
66e53929ce adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
bbracker
39efadf2cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
8c4e6baf48 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
Ross Thompson
32f0b97cd3 Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
2bf51362e2 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
9b98a499d7 some linux testbench cleanup 2021-10-25 10:04:30 -07:00
bbracker
046a78a8fc manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
36b39358c6 add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
26eead1c77 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
2cfbd888fd more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
e2e950ac0f Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
4c480a40f6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
77e2b6f9a9 Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
Katherine Parry
7c7c0f538a put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
Ross Thompson
de4ea16d32 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
David Harris
47e19d4caa moved coemark and testsBP to tests 2021-10-20 09:10:06 -07:00
Ross Thompson
d11136c406 Fixed bug with the external memory region selection. 
Updated bios program to copy just 127MB to dram.
 2021-10-19 11:23:23 -05:00
David Harris
00d8035836 Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
James E. Stine
c5b99300e7 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
869c35ba1c Fixed typo in imperas64mmu tests causing PMP tests not to run. 2021-10-14 13:42:24 -07:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
bbracker
4abc6fc915 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Ross Thompson
f6c6cb9ed2 Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Ross Thompson
bfe633d087 Partially working sd card reader. 2021-10-11 10:23:45 -05:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
James E. Stine
2b66615812 Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH 2021-10-10 15:44:01 -05:00
bbracker
a88ae5aaff use correct string formatting function 2021-10-10 10:09:59 -07:00
bbracker
6fce53d146 make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00
Kip Macsai-Goren
303beaa083 updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully. 2021-10-08 15:40:18 -07:00
David Harris
3d0383c154 moved fp vectors into vectors subdirectory 2021-10-07 23:28:06 -04:00
David Harris
6dd85b80a2 Included TestFloat and SoftFloat 2021-10-07 23:03:45 -04:00
James E. Stine
28e147bb19 update scripts 2021-10-07 15:14:54 -05:00
James E. Stine
8429078d4f TV for conversion and compare 2021-10-06 14:38:32 -05:00
James E. Stine
93668b5185 Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
James E. Stine
2afa6e7a6e Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included 2021-10-06 08:56:01 -05:00
Skylar Litz
5bcae393c9 added delayed MIP signal 2021-10-04 18:23:31 -04:00
Ross Thompson
8653a87e24 Added more debug flags. 2021-10-03 11:41:21 -05:00
David Harris
48e33c79a9 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
2ae51d1852 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
fbe6e41169 Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
e11c565a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit fec96218f6.
 2021-09-30 20:45:26 -04:00
David Harris
caa36f267d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
Ross Thompson
fca9b9e593 Movied tristate to test bench level. 2021-09-30 11:27:42 -05:00
Ross Thompson
cefbcd1b0c Partially sd card read on fpga. 2021-09-30 11:23:09 -05:00
David Harris
42d573be57 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
fec96218f6 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
Ross Thompson
7ca801113e Added debugging directives to system verilog. 2021-09-27 13:57:46 -05:00
bbracker
7117c0493c condense testbench code; debug_level of 0 means don't check at all 2021-09-27 03:03:11 -04:00
Ross Thompson
7d749b201b added support to due partial fpga simulation. 2021-09-26 15:00:00 -05:00
Ross Thompson
4d1b02c068 Merge branch 'main' into fpga 2021-09-26 13:22:53 -05:00
Ross Thompson
c917f14b6b Almost done writting driver for flash card reader. 2021-09-25 19:05:07 -05:00
Ross Thompson
69674f272a We now have a rough sdc read routine. 2021-09-25 17:51:38 -05:00
Ross Thompson
44196af61a Have program which checks for sdc init and issues read, but read done is 
not correctly being read back by the software.  The error is in how the
sdc indicates busy.
 2021-09-24 15:53:38 -05:00
Ross Thompson
4f7bc1be48 Added either the sdModel or constant driver for the SDC ports in all test benches. 2021-09-24 12:31:51 -05:00
Ross Thompson
9fdb1d3cc9 setup so the sdc does not need to load a model in the imperas test bench. 2021-09-24 11:30:52 -05:00
Ross Thompson
c644e940c2 Updated Imperas test bench to work with the SDC reader. 2021-09-24 11:22:54 -05:00
bbracker
3f96ff0ac0 switch testbench-linux's interrupts from xcause to mip and improve warning messages 2021-09-22 12:33:11 -04:00
bbracker
ff5379fd95 fix regression 2021-09-15 17:30:59 -04:00
David Harris
92385a1d51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-13 12:41:07 -04:00
David Harris
9fa048980d Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
Ross Thompson
cd6d1e0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-13 09:41:34 -05:00
David Harris
7be1160a48 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
Ross Thompson
296da4f437 FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
David Harris
12bd351edf Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
6550f38af9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
bbracker
bb84354a47 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
bbracker
f8272c45d1 make testbench successfully deactivate TimerIntM so as to create a nice pulse 2021-09-07 15:36:47 -04:00
bbracker
da9a366d20 No longer forcing CSRReadValM because that can feedback to corrupt some CSRs 2021-09-06 22:59:54 -04:00
bbracker
b3bc3cf6d0 modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations) 2021-09-04 19:49:26 -04:00
Ross Thompson
86fc632790 Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
e9a1dc90f6 Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
fe378f2692 Added function tracking to linux test bench. 2021-08-24 11:08:46 -05:00
Ross Thompson
c31b7b4dc5 Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
2825074114 Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
Ross Thompson
6c57002d0e Added logic to linux test bench to not stop simulation on csr write faults. 2021-08-15 11:13:32 -05:00
Ross Thompson
55fda4de62 Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Ross Thompson
32db21659f Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token. 2021-08-13 14:53:43 -05:00
Ross Thompson
e141a00934 Cleaned up the linux testbench by removing old code and signals. 
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
 2021-08-13 14:39:05 -05:00
Ross Thompson
9ff9c4dff9 Minor cleanup of the linux test bench. 2021-08-12 11:14:55 -05:00