forked from Github_Repos/cvw
fix testbench interrupt timing
This commit is contained in:
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parent
0cc71f1dec
commit
0c7681b942
@ -60,20 +60,26 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
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add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/textE
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add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName
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add wave -noupdate -expand -group {WriteBack stage} /testbench/textW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -484,7 +490,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/p
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/line
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
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add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
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@ -510,7 +515,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
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add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
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add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0}
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WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {5672440 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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@ -526,4 +531,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {182 ns} {330 ns}
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WaveRestoreZoom {5672937 ns} {5673085 ns}
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@ -103,30 +103,35 @@ module testbench();
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string checkpointDir;
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logic [1:0] initPriv;
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// Signals used to parse the trace file
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integer data_file_all;
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string name;
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integer matchCount;
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string line;
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logic [`XLEN-1:0] ExpectedPCM;
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logic [31:0] ExpectedInstrM;
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string textM;
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string token;
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string ExpectedTokens [31:0];
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integer index;
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integer StartIndex, EndIndex;
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integer TokenIndex;
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integer MarkerIndex;
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integer NumCSRM;
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`define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \
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integer traceFile``STAGE; \
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integer matchCount``STAGE; \
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string line``STAGE; \
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string token``STAGE; \
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string ExpectedTokens``STAGE [31:0]; \
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integer index``STAGE; \
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integer StartIndex``STAGE, EndIndex``STAGE; \
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integer TokenIndex``STAGE; \
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integer MarkerIndex``STAGE; \
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integer NumCSR``STAGE; \
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logic [`XLEN-1:0] ExpectedPC``STAGE; \
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logic [31:0] ExpectedInstr``STAGE; \
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string text``STAGE; \
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string MemOp``STAGE; \
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string RegWrite``STAGE; \
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integer ExpectedRegAdr``STAGE; \
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logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
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logic [`XLEN-1:0] ExpectedMemAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
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string ExpectedCSRArray``STAGE[10:0]; \
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logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
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`DECLARE_TRACE_SCANNER_SIGNALS(E)
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`DECLARE_TRACE_SCANNER_SIGNALS(M)
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integer NextMIPexpected;
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integer NextMepcExpected;
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// Memory stage expected values from trace
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logic checkInstrM;
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integer MIPexpected;
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string RegWriteM;
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integer ExpectedRegAdrM;
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logic [`XLEN-1:0] ExpectedRegValueM;
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string MemOpM;
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logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM;
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string ExpectedCSRArrayM[10:0];
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logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0];
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string name;
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logic [`AHBW-1:0] readDataExpected;
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// Write back stage expected values from trace
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logic checkInstrW;
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@ -148,6 +153,11 @@ module testbench();
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integer NumCSRPostWIndex;
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logic [`XLEN-1:0] InstrCountW;
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integer RequestDelayedMIP;
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integer ForceMIPFuture;
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integer CSRIndex;
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longint MepcExpected;
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integer CheckMIPFutureE;
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integer CheckMIPFutureM;
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// Useful Aliases
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`define RF dut.hart.ieu.dp.regf.rf
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`define PC dut.hart.ifu.pcreg.q
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@ -292,13 +302,15 @@ module testbench();
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ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
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if (CHECKPOINT==0) begin // normal
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$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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InstrCountW = '0;
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end else begin // checkpoint
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$sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
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checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir};
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$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM);
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data_file_all = $fopen({checkpointDir,"all.txt"}, "r");
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traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
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traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
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InstrCountW = CHECKPOINT;
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// manual checkpoint initializations that don't neatly fit into MACRO
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force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
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@ -319,8 +331,12 @@ module testbench();
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release `INSTRET;
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release `CURR_PRIV;
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end
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// Get the E-stage trace reader ahead of the M-stage trace reader
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matchCountE = $fgets(lineE,traceFileE);
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end
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////// CORE /////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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@ -332,94 +348,158 @@ module testbench();
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// on the next falling edge the expected state is compared to the wally state.
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// step 0: read the expected state
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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`define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \
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// always check PC, instruction bits \
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if (checkInstrM) begin \
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// read 1 line of the trace file \
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matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \
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if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
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// extract PC, Instr \
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matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \
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\
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// for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. \
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// strtok was the best idea but it cannot be used correctly as system verilog does not have null \
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// terminated strings. \
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\
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// Just going to do this char by char. \
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StartIndex``STAGE = 0; \
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TokenIndex``STAGE = 0; \
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//$display("len = %d", line``STAGE.len()); \
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for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \
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//$display("char = %s", line``STAGE[index]); \
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if (line``STAGE[index``STAGE] == " " || line``STAGE[index``STAGE] == "\n") begin \
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EndIndex``STAGE = index``STAGE; \
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ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \
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//$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \
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StartIndex``STAGE = EndIndex``STAGE + 1; \
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TokenIndex``STAGE++; \
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end \
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end \
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\
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MarkerIndex``STAGE = 3; \
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NumCSR``STAGE = 0; \
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MemOp``STAGE = ""; \
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RegWrite``STAGE = ""; \
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\
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#2; \
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\
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while(TokenIndex``STAGE > MarkerIndex``STAGE) begin \
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// parse the GPR \
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if (ExpectedTokens``STAGE[MarkerIndex``STAGE] == "GPR") begin \
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RegWrite``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
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matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%d", ExpectedRegAdr``STAGE); \
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matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedRegValue``STAGE); \
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MarkerIndex``STAGE += 3; \
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// parse memory address, read data, and/or write data \
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end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \
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MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
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matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedMemAdr``STAGE); \
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matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \
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matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \
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MarkerIndex``STAGE += 4; \
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// parse CSRs, because there are 1 or more CSRs after the CSR token \
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// we check if the CSR token or the number of CSRs is greater than 0. \
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// if so then we want to parse for a CSR. \
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end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" || NumCSR``STAGE > 0) begin \
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if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \
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// all additional CSR's won't have this token. \
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MarkerIndex``STAGE++; \
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end \
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matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \
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matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \
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MarkerIndex``STAGE += 2; \
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if(`"STAGE`"=="E") begin \
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// match MIP to QEMU's because interrupts are imprecise \
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if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "mip") begin \
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CheckMIPFutureE = 1; \
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NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
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end \
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// $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); \
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// $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); \
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// // if PC does not equal MEPC, request delayed MIP is True \
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// if(ExpectedPCM != ExpectedCSRArrayM[7]) begin \
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// RequestDelayedMIP = 1; \
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// end else begin \
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// $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); \
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// MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; \
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// force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; \
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// end \
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// end \
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// $display("%tns: ExpectedCSRArrayM::: %p",$time,ExpectedCSRArrayM); \
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if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \
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$display("hello! we are here."); \
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MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \
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$display("%tns: MepcExpected: %x",$time,MepcExpected); \
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end \
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end \
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\
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NumCSR``STAGE++; \
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end \
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end \
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if(`"STAGE`"=="M") begin \
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// override on special conditions \
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if (ExpectedMemAdrM == 'h10000005) begin \
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//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); \
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force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
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end \
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if(textM.substr(0,5) == "rdtime") begin \
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//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); \
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force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
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end \
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end \
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end \
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always @(negedge clk) begin
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// always check PC, instruction bits
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if (checkInstrM) begin
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// read 1 line of the trace file
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matchCount = $fgets(line, data_file_all);
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if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line);
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// extract PC, Instr
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matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM);
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//$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM);
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`SCAN_NEW_INSTR_FROM_TRACE(E)
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end
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// for the life of me I cannot get any build in C or C++ string parsing functions/methods to work.
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// strtok was the best idea but it cannot be used correctly as system verilog does not have null
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// terminated strings.
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// Just going to do this char by char.
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StartIndex = 0;
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TokenIndex = 0;
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//$display("len = %d", line.len());
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for(index = 0; index < line.len(); index++) begin
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//$display("char = %s", line[index]);
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if (line[index] == " " || line[index] == "\n") begin
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EndIndex = index;
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ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1);
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//$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1));
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StartIndex = EndIndex + 1;
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TokenIndex++;
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end
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always @(negedge clk) begin
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`SCAN_NEW_INSTR_FROM_TRACE(M)
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end
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// MIP spoofing
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always @(posedge clk) begin
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#1;
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if(CheckMIPFutureE) CheckMIPFutureE <= 0;
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CheckMIPFutureM <= CheckMIPFutureE;
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if(CheckMIPFutureM) begin
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if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin
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RequestDelayedMIP = 1;
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$display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
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end else begin // update MIP immediately
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$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
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MIPexpected = NextMIPexpected;
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force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
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end
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MarkerIndex = 3;
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NumCSRM = 0;
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MemOpM = "";
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RegWriteM = "";
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#2;
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while(TokenIndex > MarkerIndex) begin
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// parse the GPR
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if (ExpectedTokens[MarkerIndex] == "GPR") begin
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RegWriteM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM);
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MarkerIndex += 3;
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// parse memory address, read data, and/or write data
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end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin
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MemOpM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM);
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM);
|
||||
MarkerIndex += 4;
|
||||
// parse CSRs, because there are 1 or more CSRs after the CSR token
|
||||
// we check if the CSR token or the number of CSRs is greater than 0.
|
||||
// if so then we want to parse for a CSR.
|
||||
end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin
|
||||
if(ExpectedTokens[MarkerIndex] == "CSR") begin
|
||||
// all additional CSR's won't have this token.
|
||||
MarkerIndex++;
|
||||
end
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]);
|
||||
matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]);
|
||||
MarkerIndex += 2;
|
||||
// match MIP to QEMU's because interrupts are imprecise
|
||||
if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin
|
||||
$display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]);
|
||||
$display("%tn: ExpectedPCM = %x",$time,ExpectedPCM);
|
||||
// if PC does not equal MEPC, request delayed MIP is True
|
||||
if(ExpectedPCM != ExpectedCSRArrayM[7]) begin
|
||||
RequestDelayedMIP = 1;
|
||||
end else begin
|
||||
$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
|
||||
MIPexpected = ExpectedCSRArrayValueM[NumCSRM];
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
end
|
||||
end
|
||||
NumCSRM++;
|
||||
end
|
||||
end
|
||||
// override on special conditions
|
||||
if (ExpectedMemAdrM == 'h10000005) begin
|
||||
//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW);
|
||||
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
|
||||
end
|
||||
if(textM.substr(0,5) == "rdtime") begin
|
||||
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW);
|
||||
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM;
|
||||
$display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
|
||||
$display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
|
||||
$display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM);
|
||||
$display("%tn: MepcExpected = %x",$time,MepcExpected);
|
||||
$display("%tn: ExpectedPCM = %x",$time,ExpectedPCM);
|
||||
// if PC does not equal MEPC, request delayed MIP is True
|
||||
$display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM));
|
||||
$display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]);
|
||||
$display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
|
||||
|
||||
if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin
|
||||
RequestDelayedMIP = 1;
|
||||
$display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
|
||||
end else begin
|
||||
$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
|
||||
MIPexpected = NextMIPexpected;
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
end
|
||||
end
|
||||
if(RequestDelayedMIP) begin
|
||||
$display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW);
|
||||
$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
|
||||
$display("%tns: MepcExpected %x",$time,MepcExpected);
|
||||
MIPexpected = NextMIPexpected;
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
$display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW);
|
||||
RequestDelayedMIP = 0;
|
||||
end
|
||||
end
|
||||
|
||||
// step 1: register expected state into the write back stage.
|
||||
@ -449,7 +529,7 @@ module testbench();
|
||||
ExpectedMemWriteDataW <= '0;
|
||||
ExpectedMemReadDataW <= '0;
|
||||
NumCSRW <= '0;
|
||||
end else begin
|
||||
end else if (dut.hart.ieu.c.InstrValidM) begin
|
||||
ExpectedPCW <= ExpectedPCM;
|
||||
ExpectedInstrW <= ExpectedInstrM;
|
||||
textW <= textM;
|
||||
@ -484,12 +564,6 @@ module testbench();
|
||||
// step2: make all checks in the write back stage.
|
||||
assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
|
||||
always @(negedge clk) begin
|
||||
if(RequestDelayedMIP) begin
|
||||
$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]);
|
||||
MIPexpected = ExpectedCSRArrayValueW[NumCSRM];
|
||||
force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
|
||||
RequestDelayedMIP = 0;
|
||||
end
|
||||
// always check PC, instruction bits
|
||||
if (checkInstrW) begin
|
||||
InstrCountW += 1;
|
||||
@ -521,7 +595,7 @@ module testbench();
|
||||
if(MemOpW == "MemR" || MemOpW == "MemRW") begin
|
||||
if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
||||
`checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW)
|
||||
end else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin
|
||||
end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin
|
||||
if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
|
||||
`checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user