forked from Github_Repos/cvw
add checkpointing to linux testbench
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@ -63,7 +63,8 @@ module csr #(parameter
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output logic STATUS_MIE, STATUS_SIE,
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input logic [4:0] SetFflagsM,
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output logic [2:0] FRM_REGW,
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// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
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@ -103,7 +103,8 @@ module csrc #(parameter
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logic WriteCYCLEM, WriteINSTRETM;
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logic WriteHPMCOUNTER3M, WriteHPMCOUNTER4M;
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logic [4:0] CounterNumM;
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logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW;
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logic [`XLEN-1:0] HPMCOUNTER_REGW [`COUNTERS-1:3];
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logic [`XLEN-1:0] HPMCOUNTERH_REGW [`COUNTERS-1:3];
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logic InstrValidNotFlushedM;
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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@ -51,7 +51,7 @@ module csrsr (
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// Lower privilege status registers are a subset of the full status register
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// *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec
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generate
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if (`XLEN==64) begin// RV64
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if (`XLEN==64) begin: csrsr64 // RV64
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assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0,
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STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
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@ -67,7 +67,7 @@ module csrsr (
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/* STATUS_XS, STATUS_FS, /*STATUS_MPP, 8'b0, */
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/*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE,
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/*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE};
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end else begin// RV32
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end else begin: csrsr32 // RV32
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assign MSTATUS_REGW = {STATUS_SD, 8'b0,
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STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
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@ -27,7 +27,7 @@
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`include "wally-config.vh"
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`define DEBUG_TRACE 0
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`define DEBUG_TRACE 2
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// Debug Levels
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// 0: don't check against QEMU
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// 1: print disagreements with QEMU, but only halt on PCW disagreements
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@ -35,10 +35,16 @@
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// 3: halt on all disagreements with QEMU
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// 4: print memory accesses whenever they happen
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// 5: print everything
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//
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// uncomment the following line to activate checkpoint
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`define CHECKPOINT 8500000
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`ifdef CHECKPOINT
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`define CHECKPOINT_DIR {`LINUX_TEST_VECTORS, "checkpoint", `"`CHECKPOINT`", "/"}
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`endif
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module testbench();
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*8700000; // # of instructions at which to turn on waves in graphical sim
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0; // # of instructions at which to turn on waves in graphical sim
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string ProgramAddrMapFile, ProgramLabelMapFile;
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///////////////////////////////////////////////////////////////////////////////
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@ -91,9 +97,8 @@ module testbench();
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// Write Back trace signals
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logic checkInstrW;
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//integer RegAdr;
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integer fault;
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logic TrapW;
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integer fault;
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logic TrapW;
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// Signals used to parse the trace file.
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logic checkInstrM;
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@ -141,7 +146,6 @@ module testbench();
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// ------
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// Macros
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// ------
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`define CSRwarn(CSR) \
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begin \
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
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@ -158,14 +162,21 @@ module testbench();
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end
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initial begin
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data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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InstrCountW = '0;
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`ifdef CHECKPOINT
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data_file_all = $fopen({`CHECKPOINT_DIR,"all.txt"}, "r");
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`else
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data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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`endif
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`ifdef CHECKPOINT
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InstrCountW = `CHECKPOINT;
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`else
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InstrCountW = '0;
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`endif
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force dut.hart.priv.SwIntM = 0;
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force dut.hart.priv.TimerIntM = 0;
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force dut.hart.priv.ExtIntM = 0;
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end
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
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@ -345,7 +356,7 @@ module testbench();
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end
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if (RegWriteW == "GPR") begin
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`checkEQ("Reg Write Address",dut.hart.ieu.dp.regf.a3,ExpectedRegAdrW)
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$sprintf(name,"RF[%02d]",ExpectedRegAdrW);
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$sformat(name,"RF[%02d]",ExpectedRegAdrW);
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`checkEQ(name, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
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end
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if (MemOpW.substr(0,2) == "Mem") begin
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@ -394,21 +405,163 @@ module testbench();
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.ProgramLabelMapFile(ProgramLabelMapFile));
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////////////// Testbench Core ///////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////// Testbench Core /////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// --------------
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// Initialization
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// --------------
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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/*`ifdef CHECKPOINT
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var [`XLEN-1:0] initRF[31:1];
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var [`COUNTERS-1:3][`XLEN-1:0] initHPMCOUNTER;
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var [7:0][`PMP_ENTRIES-1:0] initPMPCFG;
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var [`XLEN-1:0][`PMP_ENTRIES-1:0] initPMPADDR;
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var initMIDELEG, initMCAUSE, initMCOUNTEREN, initMEDELEG, initMEPC, initMTVEC, initMIE,
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initMIP, initMSCRATCH, initMSTATUS, initSCAUSE, initSSCRATCH, initSATP, initSCOUNTEREN,
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initSEPC, initSTVEC;
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`endif*/
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`ifdef CHECKPOINT
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`define RF dut.hart.ieu.dp.regf.rf
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`define PC dut.hart.ifu.pcreg.q
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`define CSR_BASE dut.hart.priv.csr.genblk1
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`define HPMCOUNTER `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
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`define PMP_BASE `CSR_BASE.csrm.genblk4
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`define PMPCFG genblk2.PMPCFGreg.q
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`define PMPADDR PMPADDRreg.q
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`define MEDELEG `CSR_BASE.csrm.genblk1.MEDELEGreg.q
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`define MIDELEG `CSR_BASE.csrm.genblk1.MIDELEGreg.q
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`define MIE `CSR_BASE.csri.MIE_REGW
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`define MIP `CSR_BASE.csri.MIP_REGW
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`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
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`define SCAUSE `CSR_BASE.csrs.genblk1.SCAUSEreg.q
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`define MEPC `CSR_BASE.csrm.MEPCreg.q
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`define SEPC `CSR_BASE.csrs.genblk1.SEPCreg.q
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`define MCOUNTEREN `CSR_BASE.csrm.genblk3.MCOUNTERENreg.q
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`define SCOUNTEREN `CSR_BASE.csrs.genblk1.genblk3.SCOUNTERENreg.q
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`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
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`define SSCRATCH `CSR_BASE.csrs.genblk1.SSCRATCHreg.q
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`define MTVEC `CSR_BASE.csrm.MTVECreg.q
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`define STVEC `CSR_BASE.csrs.genblk1.STVECreg.q
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`define SATP `CSR_BASE.csrs.genblk1.genblk2.SATPreg.q
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`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
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`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
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`define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT
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`define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT
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`define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT
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`define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT
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`define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT
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`define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT
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`define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP
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`define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP
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`define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE
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`define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE
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`define STATUS_UPIE `CSR_BASE.csrsr.STATUS_UPIE
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`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
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`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
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`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
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`define CURR_PRIV dut.hart.priv.privmodereg.q
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`define INSTRET dut.hart.priv.csr.genblk1.counters.genblk1.genblk2.INSTRETreg.q
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`define INIT_CHECKPOINT_VAL(SIGNAL_BASE,SIGNAL,DIM,LARGE_INDEX,SMALL_INDEX) \
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logic DIM init``SIGNAL [LARGE_INDEX:SMALL_INDEX]; \
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initial $readmemh({`CHECKPOINT_DIR,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \
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for (i=SMALL_INDEX; i<LARGE_INDEX+1; i=i+1) begin \
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initial begin \
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force `SIGNAL_BASE[i].`SIGNAL = init``SIGNAL[i]; \
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#23; \
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release `SIGNAL_BASE[i].`SIGNAL; \
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end \
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end
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`define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,FIRST_INDEX,LAST_INDEX) \
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logic DIM init``SIGNAL [FIRST_INDEX:LAST_INDEX]; \
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initial begin \
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$readmemh({`CHECKPOINT_DIR,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \
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force `SIGNAL = init``SIGNAL; \
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#23; \
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release `SIGNAL; \
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end
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`define INIT_CHECKPOINT_VAL_SINGLE(SIGNAL,DIM) \
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logic DIM init``SIGNAL[0:0]; \
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initial begin \
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$readmemh({`CHECKPOINT_DIR,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \
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force `SIGNAL = init``SIGNAL[0]; \
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#23; \
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release `SIGNAL; \
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end
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`define MAKE_INIT_SIGNAL(SIGNAL,DIM) \
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logic DIM init``SIGNAL[0:0]; \
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initial begin \
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$readmemh({`CHECKPOINT_DIR,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \
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end
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generate
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genvar i;
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`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
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`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
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`INIT_CHECKPOINT_VAL(PMP_BASE, PMPCFG, [7:0],`PMP_ENTRIES-1,0);
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`INIT_CHECKPOINT_VAL(PMP_BASE, PMPADDR, [`XLEN-1:0],`PMP_ENTRIES-1,0);
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endgenerate
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`INIT_CHECKPOINT_VAL_SINGLE(PC, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MEDELEG, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MIE, [11:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MIP, [11:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MCAUSE, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(SCAUSE, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MEPC, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(SEPC, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MCOUNTEREN, [31:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(SCOUNTEREN, [31:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MSCRATCH, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(SSCRATCH, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(MTVEC, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(STVEC, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL_SINGLE(SATP, [`XLEN-1:0]);
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`MAKE_INIT_SIGNAL(MSTATUS, [`XLEN-1:0]);
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initial begin
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force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
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force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11];
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force {`STATUS_SPP,`STATUS_MPIE} = initMSTATUS[0][8:7];
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force {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE} = initMSTATUS[0][5:3];
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force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0];
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#23;
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release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV};
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release {`STATUS_FS,`STATUS_MPP};
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release {`STATUS_SPP,`STATUS_MPIE};
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release {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE};
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release {`STATUS_SIE,`STATUS_UIE};
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end
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logic [1:0] initPriv;
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assign initPriv = (initPC[0][`XLEN-1]) ? 2'h2 : 2'h3; // *** a hacky way to detect privilege level
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initial begin
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force `CURR_PRIV = initPriv;
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#23;
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release `CURR_PRIV;
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end
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initial begin
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force `INSTRET = `CHECKPOINT;
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#23;
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release `INSTRET;
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end
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`endif
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initial begin
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reset <= 1; # 22; reset <= 0;
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$stop;
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end
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// initial loading of memories
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initial begin
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$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
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$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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`ifdef CHECKPOINT
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$readmemh({`CHECKPOINT_DIR,"ram.txt"}, dut.uncore.dtim.RAM);
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`else
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$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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`endif
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
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ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
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