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Merge branch 'main' into fpga

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This commit is contained in:
Ross Thompson 2021-10-22 16:09:16 -05:00
commit 77e2b6f9a9
8 changed files with 399 additions and 291 deletions
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2
wally-pipelined/config/rv64g/wally-config.vh
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@ -36,7 +36,7 @@
`define XLEN 64
// MISA RISC-V configuration per specification
`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
`define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1
`define COUNTERS 32

2
wally-pipelined/src/fpu/divconv.sv
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@ -88,7 +88,7 @@ module divconv (
mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const);
// CPA (from CSA)/Remainder addition/subtraction
assign {cout1, mul_out} = (mcand*mplier) + constant + {118'b0, muxr_out};
assign {cout1, mul_out} = (mcand*mplier) + constant + {119'b0, muxr_out};
// Assuming [1,2) - q1
assign {cout2, q_out1} = regb_out + q_const;

19
wally-pipelined/src/fpu/divconv_pipe.sv
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@ -50,6 +50,7 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
supply0 vss;
logic [59:0] muxa_out, muxb_out;
logic muxr_out;
logic [10:0] ia_div, ia_sqrt;
logic [59:0] ia_out;
logic [119:0] mul_out;
@ -67,8 +68,8 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
// Check if exponent is odd for sqrt
// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
assign d2 = (exp_odd&op_type) ? {vss,d,6'h0} : {d,7'h0};
assign n2 = op_type ? d2 : {n,7'h0};
assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0};
assign n2 = op_type ? d2 : {n, 7'h0};
// IA div/sqrt
sbtm_div ia1 (d[52:41], ia_div);
@ -137,7 +138,7 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
flopenr #(60) regpE (clk, reset, load_regp, qm_const, qm_const_pipe);
// CPA (from CSA)/Remainder addition/subtraction
assign {cout1, mul_out} = Sum_pipe + Carry_pipe + muxr_pipe;
assign mul_out = Sum_pipe + Carry_pipe + {119'h0, muxr_pipe};
// One's complement instead of two's complement (for hw efficiency)
assign three = {~mul_out[118] , mul_out[118], ~mul_out[117:59]};
mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type_pipe, twocmp_out);
@ -154,13 +155,13 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
flopenr #(60) rego (clk, reset, regs_pipe, qm_const_pipe, qm_const_pipe2);
// Assuming [1,2) - q1
assign {cout2, q_out1} = regb_out + q_const;
assign {cout3, qp_out1} = regb_out + qp_const;
assign {cout4, qm_out1} = regb_out + qm_const + 1'b1;
assign q_out1 = regb_out + q_const;
assign qp_out1 = regb_out + qp_const;
assign qm_out1 = regb_out + qm_const + 1'b1;
// Assuming [0.5,1) - q0
assign {cout5, q_out0} = {regb_out[58:0], 1'b0} + q_const;
assign {cout6, qp_out0} = {regb_out[58:0], 1'b0} + qp_const;
assign {cout7, qm_out0} = {regb_out[58:0], 1'b0} + qm_const + 1'b1;
assign q_out0 = {regb_out[58:0], 1'b0} + q_const;
assign qp_out0 = {regb_out[58:0], 1'b0} + qp_const;
assign qm_out0 = {regb_out[58:0], 1'b0} + qm_const + 1'b1;
// Stage 3
// Assuming [1,2)

31
wally-pipelined/src/fpu/fma.sv
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@ -381,15 +381,10 @@ module posloa(
// Apply function to determine Leading pattern
logic [3*`NF+6:0] pf;
assign pf = T^{Z[3*`NF+5:0], 1'b0};
logic [3*`NF+6:0] f;
assign f = T^{Z[3*`NF+5:0], 1'b0};
logic [8:0] i;
always_comb begin
i = 0;
while (~pf[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one
PCnt = i;
end
lzc lzc(.f, .Cnt(PCnt));
endmodule
@ -410,17 +405,23 @@ module negloa(
logic [3*`NF+6:0] f;
assign f = T^{~Z, 1'b0};
logic [8:0] i;
always_comb begin
i = 0;
while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one
NCnt = i;
end
lzc lzc(.f, .Cnt(NCnt));
endmodule
module lzc(
input logic [3*`NF+6:0] f,
output logic [8:0] Cnt // normalization shift count for the negitive result
);
logic [8:0] i;
always_comb begin
i = 0;
while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one
Cnt = i;
end
endmodule

67
wally-pipelined/src/fpu/fpdiv_pipe.sv
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@ -42,6 +42,7 @@ module fpdiv_pipe (
output logic done,
output logic FDivBusyE,
output logic load_preload,
output logic [63:0] AS_Result,
output logic [4:0] Flags);
@ -53,6 +54,7 @@ module fpdiv_pipe (
logic [63:0] IntValue;
logic [12:0] exp1, exp2, expF;
logic [14:0] exp_pre_diff;
logic [12:0] exp_diff, bias;
logic [13:0] exp_sqrt;
@ -78,13 +80,18 @@ module fpdiv_pipe (
logic [2:0] sel_muxa, sel_muxb;
logic sel_muxr;
logic load_rega, load_regb, load_regc, load_regd, load_regr;
logic load_regp;
logic donev, sel_muxrv, sel_muxsv;
logic [1:0] sel_muxav, sel_muxbv;
logic load_regav, load_regbv, load_regcv;
logic load_regrv, load_regsv;
logic load_regp, load_regs;
logic exp_odd, exp_odd1;
logic start1;
logic P1;
logic op_type1;
logic [12:0] expF1;
logic [52:0] mantissaA1;
logic [52:0] mantissaB1;
logic [2:0] sel_inv1;
logic signResult1;
logic Invalid1;
// op_type : fdiv=0, fsqrt=1
assign Float1 = op1;
@ -94,11 +101,9 @@ module fpdiv_pipe (
exception_div exc1 (.A(Float1), .B(Float2), .op_type, .Ztype(sel_inv), .Invalid);
// Determine Sign/Mantissa
assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type;
assign signResult = ((Float1[63]^Float2[63])&~op_type);
assign mantissaA = {vdd, Float1[51:0]};
assign mantissaB = {vdd, Float2[51:0]};
// Early-ending detection
assign early_detection = |mantissaB[31:0];
// Perform Exponent Subtraction - expA - expB + Bias
assign exp1 = {2'b0, Float1[62:52]};
@ -106,26 +111,15 @@ module fpdiv_pipe (
// bias : DP = 2^{11-1}-1 = 1023
assign bias = {3'h0, 10'h3FF};
// Divide exponent
assign {exp_cout1, open, exp_diff} = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias};
assign exp_pre_diff = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias};
assign exp_diff = exp_pre_diff[12:0];
// Sqrt exponent (check if exponent is odd)
assign exp_odd = Float1[52] ? vss : vdd;
assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd};
assign exp_odd = Float1[52] ? 1'b0 : 1'b1;
assign exp_sqrt = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd};
// Choose correct exponent
assign expF = op_type ? exp_sqrt[13:1] : exp_diff;
logic exp_odd1;
logic P1;
logic op_type1;
logic [12:0] expF1;
logic [52:0] mantissaA1;
logic [52:0] mantissaB1;
logic [2:0] sel_inv1;
logic DenormIn1;
logic signResult1;
logic Invalid1;
flopenr #(1) rega (clk, reset, 1'b1, exp_odd, exp_odd1);
flopenr #(1) regb (clk, reset, 1'b1, P, P1);
flopenr #(1) regc (clk, reset, 1'b1, op_type, op_type1);
@ -134,33 +128,32 @@ module fpdiv_pipe (
flopenr #(53) regf (clk, reset, 1'b1, mantissaB, mantissaB1);
flopenr #(1) regg (clk, reset, 1'b1, start, start1);
flopenr #(3) regh (clk, reset, 1'b1, sel_inv, sel_inv1);
flopenr #(1) regi (clk, reset, 1'b1, DenormIn, DenormIn1);
flopenr #(1) regj (clk, reset, 1'b1, signResult, signResult1);
flopenr #(1) regk (clk, reset, 1'b1, Invalid, Invalid1);
// Main Goldschmidt/Division Routine
divconv_pipe goldy (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out,
regr_out, mantissaB1, mantissaA1,
sel_muxa, sel_muxb, sel_muxr, reset, clk,
load_rega, load_regb, load_regc, load_regd,
load_regr, load_regs, load_regp,
P1, op_type1, exp_odd1);
divconv_pipe goldy (.q1, .qm1, .qp1, .q0, .qm0, .qp0,
.rega_out, .regb_out, .regc_out, .regd_out,
.regr_out, .d(mantissaB1), .n(mantissaA1),
.sel_muxa, .sel_muxb, .sel_muxr, .reset, .clk,
.load_rega, .load_regb, .load_regc, .load_regd,
.load_regr, .load_regs, .load_regp,
.P(P), .op_type(op_type1), .exp_odd(exp_odd1));
// FSM : control divider
fsm_fpdiv_pipe control (.clk, .reset, .start, .op_type, .P,
fsm_fpdiv_pipe control (.clk, .reset, .start(start), .op_type(op_type1), .P(P),
.done, .load_rega, .load_regb, .load_regc, .load_regd,
.load_regr, .load_regs, .load_regp,
.load_regr, .load_regs, .load_regp, .load_preload,
.sel_muxa, .sel_muxb, .sel_muxr, .divBusy(FDivBusyE));
// Round the mantissa to a 52-bit value, with the leading one
// removed. The rounding units also handles special cases and
// set the exception flags.
rounder_div round1 (.rm, .P, .OvEn, .UnEn, .exp_diff(expF),
.sel_inv, .Invalid, .SignR(signResult),
rounder_div round1 (.rm, .P(P), .OvEn(1'b0), .UnEn(1'b0), .exp_diff(expF1),
.sel_inv(sel_inv1), .Invalid(Invalid1), .SignR(signResult1),
.Float1(op1), .Float2(op2),
.XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ,
.XInfQ, .YInfQ, .op_type,
.XInfQ, .YInfQ, .op_type(op_type1),
.q1, .qm1, .qp1, .q0, .qm0, .qp0, .regr_out,
.Result, .Flags(FlagsIn));

138
wally-pipelined/src/fpu/fpu.sv
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@ -66,67 +66,71 @@ module fpu (
logic FDivStartD, FDivStartE; // Start division or squareroot
logic FWriteIntD; // Write to integer register
logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
logic [1:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select the result written to FP register
logic [2:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
logic [2:0] FResSelD, FResSelE, FResSelM; // Select one of the results that finish in the memory stage
logic [1:0] FIntResSelD, FIntResSelE, FIntResSelM; // Select the result written to the integer resister
logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
logic [1:0] FResultSelD, FResultSelE; // Select the result written to FP register
logic [1:0] FResultSelM, FResultSelW; // Select the result written to FP register
logic [2:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
logic [2:0] FResSelD, FResSelE, FResSelM; // Select one of the results that finish in the memory stage
logic [1:0] FIntResSelD, FIntResSelE; // Select the result written to the integer resister
logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
// regfile signals
logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
logic [63:0] FSrcXE, FSrcXM; // Input 1 to the various units (after forwarding)
logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
logic [63:0] FSrcXE; // Input 1 to the various units (after forwarding)
logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
// unpacking signals
logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
logic XSgnM, YSgnM; // input's sign - memory stage
logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage
logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
logic [10:0] BiasE; // bias based on precision (single=7f double=3ff - max expoent/2)
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
logic XNaNQ, YNaNQ; // is the input a NaN - divide
logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
logic XDenormE, YDenormE, ZDenormE; // is the input denormalized
logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage
logic XZeroQ, YZeroQ; // is the input zero - divide
logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
logic XInfQ, YInfQ; // is the input infinity - divide
logic XExpMaxE; // is the exponent all ones (max value)
logic XNormE; // is normal
logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
logic XSgnM, YSgnM; // input's sign - memory stage
logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage
logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
logic [10:0] BiasE; // bias based on precision (single=7f double=3ff)
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
logic XNaNQ, YNaNQ; // is the input a NaN - divide
logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
logic XDenormE, YDenormE, ZDenormE; // is the input denormalized
logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage
logic XZeroQ, YZeroQ; // is the input zero - divide
logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
logic XInfQ, YInfQ; // is the input infinity - divide
logic XExpMaxE; // is the exponent all ones (max value)
logic XNormE; // is normal
logic FmtQ;
logic FDivStartQ;
logic FOpCtrlQ;
// result and flag signals
logic [63:0] FDivResM, FDivResW; // divide/squareroot result
logic [4:0] FDivFlgM, FDivFlgW; // divide/squareroot flags
logic [63:0] FMAResM, FMAResW; // FMA/multiply result
logic [4:0] FMAFlgM, FMAFlgW; // FMA/multiply result
logic [63:0] ReadResW; // read result (load instruction)
logic [63:0] CvtFpResE, CvtFpResM, CvtFpResW; // add/FP -> FP convert result
logic [4:0] CvtFpFlgE, CvtFpFlgM, CvtFpFlgW; // add/FP -> FP convert flags
logic [63:0] CvtResE, CvtResM; // FP <-> int convert result
logic [4:0] CvtFlgE, CvtFlgM; // FP <-> int convert flags //*** trim this
logic [63:0] ClassResE, ClassResM; // classify result
logic [63:0] CmpResE, CmpResM; // compare result
logic CmpNVE, CmpNVM; // compare invalid flag (Not Valid)
logic [63:0] SgnResE, SgnResM; // sign injection result
logic SgnNVE, SgnNVM; // sign injection invalid flag (Not Valid)
logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
logic [63:0] FDivResM, FDivResW; // divide/squareroot result
logic [4:0] FDivFlgM, FDivFlgW; // divide/squareroot flags
logic [63:0] FMAResM, FMAResW; // FMA/multiply result
logic [4:0] FMAFlgM, FMAFlgW; // FMA/multiply result
logic [63:0] ReadResW; // read result (load instruction)
logic [63:0] CvtFpResE, CvtFpResM, CvtFpResW; // add/FP -> FP convert result
logic [4:0] CvtFpFlgE, CvtFpFlgM, CvtFpFlgW; // add/FP -> FP convert flags
logic [63:0] CvtResE, CvtResM; // FP <-> int convert result
logic [4:0] CvtFlgE, CvtFlgM; // FP <-> int convert flags //*** trim this
logic [63:0] ClassResE, ClassResM; // classify result
logic [63:0] CmpResE, CmpResM; // compare result
logic CmpNVE, CmpNVM; // compare invalid flag (Not Valid)
logic [63:0] SgnResE, SgnResM; // sign injection result
logic SgnNVE, SgnNVM; // sign injection invalid flag (Not Valid)
logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
logic [`XLEN-1:0] FIntResE;
logic [63:0] FPUResultW; // final FP result being written to the FP register
logic [63:0] FPUResultW; // final FP result being written to the FP register
// other signals
logic FDivSqrtDoneE; // is divide done
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
logic FDivClk; // clock for divide/squareroot unit
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
logic FDivSqrtDoneE; // is divide done
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
logic FDivClk; // clock for divide/squareroot unit
logic load_preload; // enable for FF on fpdivsqrt
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
// DECODE STAGE
@ -192,20 +196,20 @@ module fpu (
.FMAFlgM, .FMAResM);
// fpdivsqrt using Goldschmidt's iteration
floprc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
.clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE));
floprc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
.clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE));
floprc #(6) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE}),
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ}),
.clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE));
fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
.reset, .clk(clk), .start(FDivStartE), .P(~FmtE), .OvEn(1'b1), .UnEn(1'b1),
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ,
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}),
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ),
.reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
// convert from signle to double and vice versa
cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);

415
wally-pipelined/src/fpu/fsm_fpdiv_pipe.sv
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File diff suppressed because it is too large Load Diff

16
wally-pipelined/testbench/tests.vh
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@ -85,10 +85,10 @@ string imperas32f[] = '{
"rv64f/I-FSW-01", "2000",
"rv64f/I-FCLASS-S-01", "2000",
"rv64f/I-FADD-S-01", "2000",
// "rv64f/I-FCVT-S-L-01", "2000",
// "rv64f/I-FCVT-S-LU-01", "2000",
// "rv64f/I-FCVT-S-W-01", "2000",
// "rv64f/I-FCVT-S-WU-01", "2000",
"rv64f/I-FCVT-S-L-01", "2000",
"rv64f/I-FCVT-S-LU-01", "2000",
"rv64f/I-FCVT-S-W-01", "2000",
"rv64f/I-FCVT-S-WU-01", "2000",
"rv64f/I-FCVT-L-S-01", "2000",
"rv64f/I-FCVT-LU-S-01", "2000",
"rv64f/I-FCVT-W-S-01", "2000",
@ -135,11 +135,11 @@ string imperas32f[] = '{
"rv64d/I-FSGNJX-D-01", "2000",
"rv64d/I-FSQRT-D-01", "2000",
"rv64d/I-FSUB-D-01", "2000",
// "rv64d/I-FCVT-D-L-01", "2000",
// "rv64d/I-FCVT-D-LU-01", "2000",
"rv64d/I-FCVT-D-L-01", "2000",
"rv64d/I-FCVT-D-LU-01", "2000",
"rv64d/I-FCVT-D-S-01", "2000",
// "rv64d/I-FCVT-D-W-01", "2000",
// "rv64d/I-FCVT-D-WU-01", "2000",
"rv64d/I-FCVT-D-W-01", "2000",
"rv64d/I-FCVT-D-WU-01", "2000",
"rv64d/I-FCVT-L-D-01", "2000",
"rv64d/I-FCVT-LU-D-01", "2000",
"rv64d/I-FCVT-S-D-01", "2000",