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add option for regression to do a partial execution of buildroot

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This commit is contained in:
bbracker 2021-10-23 13:17:30 -07:00
parent d24bece3a8
commit 3c0b0987d2
4 changed files with 33 additions and 19 deletions
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33
wally-pipelined/regression/regression-wally.py
View File

@ -10,6 +10,7 @@
# output.
#
##################################
import sys
from collections import namedtuple
TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr'])
@ -23,22 +24,22 @@ TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr'])
# edit this list to add more test cases
configs = [
#TestCase(
# name="busybear",
# cmd="vsim -do wally-busybear-batch.do -c > {}",
# grepstr="loaded 100000 instructions"
#),
TestCase(
name="buildroot",
cmd="vsim -do wally-buildroot-batch.do -c > {}",
grepstr="6300000 instructions"
),
TestCase(
name="lints",
cmd="./lint-wally &> {}",
grepstr="All lints run with no errors or warnings"
),
)
]
def getBuildrootTC(short):
INSTR_LIMIT = 100000 # multiple of 100000
MAX_EXPECTED = 6.3e6
if short:
BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+"\n!"
BRgrepstr=str(INSTR_LIMIT)+" instructions"
else:
BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do 0\n!"
BRgrepstr=str(MAX_EXPECTED)+" instructions"
return TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr)
tests64 = ["arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"]
for test in tests64:
@ -83,7 +84,15 @@ def main():
"""Run the tests and count the failures"""
# Scale the number of concurrent processes to the number of test cases, but
# max out at a limited number of concurrent processes to not overwhelm the system
TIMEOUT_DUR = 1800 # seconds
if '-all' in sys.argv:
TIMEOUT_DUR = 3600
configs.append(getBuildrootTC(short=False))
else:
TIMEOUT_DUR = 300
configs.append(getBuildrootTC(short=True))
print(configs)
try:
os.mkdir("logs")
except:

3
wally-pipelined/regression/sim-buildroot-batch
View File

@ -1,3 +1,4 @@
INSTR_LIMIT=${1:-0}
vsim -c <<!
do wally-buildroot-batch.do
do wally-buildroot-batch.do $INSTR_LIMIT
!

2
wally-pipelined/regression/wally-buildroot-batch.do
View File

@ -30,7 +30,7 @@ vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work.testbench -o workopt
vopt work.testbench -G INSTR_LIMIT=$1 -o workopt
vsim workopt -suppress 8852,12070

14
wally-pipelined/testbench/testbench-linux.sv
View File

@ -38,7 +38,9 @@
module testbench();
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*6300000; // # of instructions at which to turn on waves in graphical sim
parameter INSTR_LIMIT = 0; // # of instructions at which to stop
parameter INSTR_WAVEON = (INSTR_LIMIT > 10000) ? INSTR_LIMIT-10000 : 1; // # of instructions at which to turn on waves in graphical sim
string ProgramAddrMapFile, ProgramLabelMapFile;
///////////////////////////////////////////////////////////////////////////////
@ -343,10 +345,12 @@ module testbench();
// always check PC, instruction bits
if (checkInstrW) begin
InstrCountW += 1;
// turn on waves at certain point
if (InstrCountW == waveOnICount) $stop;
// print progress message
if (InstrCountW % 'd100000 == 0) $display("Reached %d instructions", InstrCountW);
// turn on waves
if (InstrCountW == INSTR_WAVEON) $stop;
// end sim
if ((InstrCountW == INSTR_LIMIT) && (INSTR_LIMIT!=0)) $stop;
fault = 0;
if (`DEBUG_TRACE >= 1) begin
`checkEQ("PCW",PCW,ExpectedPCW)
@ -423,8 +427,8 @@ module testbench();
initial begin
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
end