forked from Github_Repos/cvw
Added back in the csr checking logic. Added code to force timer, external, and software interrupts by using the expected values from qemu's (m/s)cause registers. Still need to prevent wally's timer interrupt. |
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.. | ||
common | ||
imperas-boottim.txt | ||
testbench-coremark_bare.sv | ||
testbench-coremark.sv | ||
testbench-imperas.sv | ||
testbench-linux.sv | ||
testbench-privileged.sv |