forked from Github_Repos/cvw
Merge branch 'main' into fpga
This commit is contained in:
commit
f6c6cb9ed2
.gitmodulesREADME.md
wally-pipelined
config
buildroot
busybear
coremark
coremark_bare
fpga
old
rv32icfd
rv64icfd
rv64imc
rv32g
rv32ic
rv64BP
rv64g
rv64ic
fpu-testfloat/FMA/tbgen
lint-wallylinux-testgen
linux-testvectors
testvector-generation
regression
linux-wave.do
old
qrun.doqrun.log
regression-wally.pyrun_sim.shsim-wallysim-wally-batchsim-wally-batch-rv32icudiv.cwally-pipelined-batch.dowally-pipelined.doqrun.out
sim-busybearsim-busybear-batchsim-fp64sim-fp64-batchsim-wally-arch-batchsim-wally-arch-batch-rv32icsim-wally-batch-muldivsim-wally-batch-rv32icsim-wally-batch-rv32icfdsim-wally-batch-rv64icfdsim-wally-muldivsim-wally-rv32icsim-wally-rv32icfdsim-wally-rv64icfdwally-arch.dowally-busybear-batch.dowally-busybear.dowally-coremark_bare.dowally-pipelined-batch-muldiv.dowally-pipelined-batch-rv32icfd.dowally-pipelined-batch-rv64icfd.dowally-pipelined-muldiv.dowally-pipelined-ross.dowally-pipelined-rv32icfd.dowally-pipelined-rv64icfd.dowally-privileged.dowave-dos
wave.dosrc
3
.gitmodules
vendored
3
.gitmodules
vendored
@ -0,0 +1,3 @@
|
||||
[submodule "sky130/sky130_osu_sc_t12"]
|
||||
path = sky130/sky130_osu_sc_t12
|
||||
url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12/
|
17
README.md
17
README.md
@ -1,2 +1,19 @@
|
||||
# riscv-wally
|
||||
Configurable RISC-V Processor
|
||||
|
||||
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
|
||||
|
||||
To use Wally on Linux:
|
||||
|
||||
git clone https://github.com/davidharrishmc/riscv-wally
|
||||
cd riscv-wally
|
||||
cd imperas-riscv-tests
|
||||
make
|
||||
cd ../addins
|
||||
git clone https://github.com/riscv-non-isa/riscv-arch-test
|
||||
|
||||
|
||||
Notes:
|
||||
Eventually download imperas-riscv-tests separately
|
||||
Move our custom tests to another directory
|
||||
Handle exe2memfile separately.
|
||||
|
@ -67,6 +67,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
|
@ -66,6 +66,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
|
@ -65,6 +65,13 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h00000000000100b0
|
||||
|
||||
|
@ -66,6 +66,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
|
@ -31,6 +31,8 @@
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
//`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
@ -65,6 +67,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
|
@ -64,6 +64,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
@ -66,6 +66,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
@ -64,6 +64,13 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
1024
wally-pipelined/config/rv32g/BTBPredictor.txt
Normal file
1024
wally-pipelined/config/rv32g/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
wally-pipelined/config/rv32g/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv32g/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
122
wally-pipelined/config/rv32g/wally-config.vh
Normal file
122
wally-pipelined/config/rv32g/wally-config.vh
Normal file
@ -0,0 +1,122 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
|
||||
// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_BLOCKLENINBITS 256
|
||||
`define DCACHE_REPLBITS 3
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define BOOTTIM_SUPPORTED 1'b1
|
||||
`define BOOTTIM_BASE 34'h00001000
|
||||
`define BOOTTIM_RANGE 34'h00000FFF
|
||||
`define TIM_SUPPORTED 1'b1
|
||||
`define TIM_BASE 34'h80000000
|
||||
`define TIM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10012000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 4
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 4
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
@ -30,11 +30,12 @@
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0)
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
@ -64,6 +65,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
@ -73,8 +78,6 @@
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define BOOTTIM_SUPPORTED 1'b1
|
||||
`define BOOTTIM_BASE 34'h00001000
|
||||
`define BOOTTIM_RANGE 34'h00000FFF
|
||||
|
@ -31,6 +31,7 @@
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
@ -68,6 +69,9 @@
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000001000
|
||||
|
1024
wally-pipelined/config/rv64g/BTBPredictor.txt
Normal file
1024
wally-pipelined/config/rv64g/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
wally-pipelined/config/rv64g/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv64g/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
126
wally-pipelined/config/rv64g/wally-config.vh
Normal file
126
wally-pipelined/config/rv64g/wally-config.vh
Normal file
@ -0,0 +1,126 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
|
||||
// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_BLOCKLENINBITS 256
|
||||
`define DCACHE_REPLBITS 3
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define BOOTTIM_SUPPORTED 1'b1
|
||||
`define BOOTTIM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTTIM_RANGE 56'h00000FFF
|
||||
`define TIM_SUPPORTED 1'b1
|
||||
`define TIM_BASE 56'h80000000
|
||||
`define TIM_RANGE 56'h7FFFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10012000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 4
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 4
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
|
@ -30,12 +30,13 @@
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
@ -65,6 +66,10 @@
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
|
@ -139,12 +139,12 @@ assign ansnan = FmtE ? &ans[`FLEN-2:`NF] && |ans[`NF-1:0] : &ans[30:23] && |ans[
|
||||
logic [8:0] NormCntE, NormCntM;
|
||||
|
||||
fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE({XAssumed1E,XFracE}), .YManE({YAssumed1E,YFracE}), .ZManE({ZAssumed1E,ZFracE}),
|
||||
.BiasE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
|
||||
.XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
|
||||
.FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE,
|
||||
.ProdExpE, .AddendStickyE, .KillProdE);
|
||||
fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM({XAssumed1E,XFracE}), .YManM({YAssumed1E,YFracE}), .ZManM({ZAssumed1E,ZFracE}), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE),
|
||||
// .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM,
|
||||
.FOpCtrlM(FOpCtrlE[2:0]), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE),
|
||||
.KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE),
|
||||
.FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM);
|
||||
|
||||
|
||||
|
@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/
|
||||
verilator=`which verilator`
|
||||
|
||||
basepath=$(dirname $0)
|
||||
for config in rv64ic rv32ic; do
|
||||
for config in rv64g rv32g; do
|
||||
echo "$config linting..."
|
||||
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv --relative-includes); then
|
||||
echo "Exiting after $config lint due to errors or warnings"
|
||||
|
@ -2,4 +2,7 @@ echo "Warning: this script will only work if your repo is on Tera"
|
||||
ln -s /courses/e190ax/buildroot_boot/all.txt all.txt
|
||||
ln -s /courses/e190ax/buildroot_boot/bootmem.txt bootmem.txt
|
||||
ln -s /courses/e190ax/buildroot_boot/ram.txt ram.txt
|
||||
ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump vmlinux.objdump
|
||||
ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.addr vmlinux.objdump.addr
|
||||
ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.lab vmlinux.objdump.lab
|
||||
echo "Done!"
|
||||
|
@ -3,4 +3,7 @@
|
||||
unlink all.txt
|
||||
unlink bootmem.txt
|
||||
unlink ram.txt
|
||||
unlink vmlinux.objdump
|
||||
unlink vmlinux.objdump.addr
|
||||
unlink vmlinux.objdump.lab
|
||||
echo "Done!"
|
||||
|
35
wally-pipelined/linux-testgen/testvector-generation/GenerateCheckpoint.sh
Executable file
35
wally-pipelined/linux-testgen/testvector-generation/GenerateCheckpoint.sh
Executable file
@ -0,0 +1,35 @@
|
||||
#!/bin/bash
|
||||
# Oftentimes this script runs so long you'll go to sleep.
|
||||
# But you don't want the script to die when your computer goes to sleep.
|
||||
# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
|
||||
# You can run "tail -f nohup.out" to see what would've
|
||||
# outputted to the terminal if you didn't use nohup
|
||||
|
||||
# use on tera.
|
||||
customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
|
||||
# use on other systems
|
||||
#customQemu="qemu-system-riscv64"
|
||||
|
||||
instrs=50000000
|
||||
|
||||
imageDir="../buildroot-image-output"
|
||||
outDir="../linux-testvectors/checkpoint$instrs"
|
||||
intermedDir="$outDir/intermediate-outputs"
|
||||
|
||||
|
||||
read -p "This scripts is going to create a checkpoint at $instrs instrs.
|
||||
Is that what you wanted? (y/n) " -n 1 -r
|
||||
echo
|
||||
if [[ $REPLY =~ ^[Yy]$ ]]
|
||||
then
|
||||
mkdir -p $outDir
|
||||
mkdir -p $intermedDir
|
||||
# Simulate QEMU, parse QEMU trace, run GDB script which logs a bunch of data at the checkpoint
|
||||
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -rtc clock=vm -icount shift=1 -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1240 -S 2>&1 1>&2 | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > $intermedDir/rawTrace.txt) & riscv64-unknown-elf-gdb -x ./checkpoint.gdb -ex "createCheckpoint $instrs \"$intermedDir\""
|
||||
# Post-Process GDB outputs
|
||||
./parseState.py "$outDir"
|
||||
./fix_mem.py "$intermedDir/ramGDB.txt" "$outDir/ram.txt"
|
||||
else
|
||||
echo "You can change the number of instructions by editing the \"instrs\" variable in this script."
|
||||
echo "Have a nice day!"
|
||||
fi
|
56
wally-pipelined/linux-testgen/testvector-generation/checkpoint.gdb
Executable file
56
wally-pipelined/linux-testgen/testvector-generation/checkpoint.gdb
Executable file
@ -0,0 +1,56 @@
|
||||
define createCheckpoint
|
||||
# GDB config
|
||||
set pagination off
|
||||
set logging overwrite on
|
||||
set logging redirect on
|
||||
set confirm off
|
||||
|
||||
# QEMU must also use TCP port 1240
|
||||
target extended-remote :1240
|
||||
|
||||
# QEMU Config
|
||||
maintenance packet Qqemu.PhyMemMode:1
|
||||
|
||||
# Argument Parsing
|
||||
set $statePath=$arg1
|
||||
set $ramPath=$arg1
|
||||
eval "set $statePath = \"%s/stateGDB.txt\"", $statePath
|
||||
eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath
|
||||
|
||||
# Symbol file
|
||||
file ../buildroot-image-output/vmlinux
|
||||
|
||||
# Step over reset vector into actual code
|
||||
stepi 1000
|
||||
# Set breakpoint for where to stop
|
||||
b do_idle
|
||||
# Proceed to checkpoint
|
||||
printf "GDB proceeding to checkpoint at %d instrs\n", $arg0
|
||||
stepi $arg0-1000
|
||||
|
||||
printf "Reached checkpoint at %d instrs\n", $arg0
|
||||
|
||||
# Log all registers to a file
|
||||
printf "GDB storing state to %s\n", $statePath
|
||||
eval "set logging file %s", $statePath
|
||||
set logging on
|
||||
info all-registers
|
||||
set logging off
|
||||
|
||||
# Log main memory to a file
|
||||
printf "GDB storing RAM to %s\n", $ramPath
|
||||
eval "set logging file %s", $ramPath
|
||||
set logging on
|
||||
x/134217728xb 0x80000000
|
||||
set logging off
|
||||
|
||||
# Continue to checkpoint; stop on the 3rd time
|
||||
# Should reach login prompt by then
|
||||
printf "GDB continuing execution to login prompt\n"
|
||||
ignore 1 2
|
||||
c
|
||||
|
||||
printf "GDB reached login prompt!\n"
|
||||
kill
|
||||
q
|
||||
end
|
@ -6,9 +6,10 @@ if len(sys.argv) != 3:
|
||||
inputFile = sys.argv[1]
|
||||
outputFile = sys.argv[2]
|
||||
if not os.path.exists(inputFile):
|
||||
sys.exit('Error input file '+inputFile+'not found')
|
||||
print('Translating '+os.path.basename(inputFile)+' to '+os.path.basename(outputFile))
|
||||
sys.exit('Error input file '+inputFile+' not found')
|
||||
print('Begin translating '+os.path.basename(inputFile)+' to '+os.path.basename(outputFile))
|
||||
with open(inputFile, 'r') as f:
|
||||
with open(outputFile, 'w') as w:
|
||||
for l in f:
|
||||
w.write(f'{"".join([x[2:] for x in l.split()[:0:-1]])}\n')
|
||||
print('Finished translating '+os.path.basename(inputFile)+' to '+os.path.basename(outputFile)+'!')
|
||||
|
@ -140,6 +140,7 @@ CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0,
|
||||
lineNum = 0
|
||||
StartLine = 0
|
||||
EndLine = 0
|
||||
numInstrs = 0
|
||||
#instructions = []
|
||||
MemAdr = 0
|
||||
lines = []
|
||||
@ -195,6 +196,10 @@ for line in fileinput.input('-'):
|
||||
lines.clear()
|
||||
#instructions.append(MoveInstrToRegWriteLst)
|
||||
PrintInstr(MoveInstrToRegWriteLst, sys.stdout)
|
||||
numInstrs +=1
|
||||
if (numInstrs % 1e4 == 0):
|
||||
sys.stderr.write('Trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n')
|
||||
sys.stderr.flush()
|
||||
lineNum += 1
|
||||
|
||||
|
||||
|
79
wally-pipelined/linux-testgen/testvector-generation/parseState.py
Executable file
79
wally-pipelined/linux-testgen/testvector-generation/parseState.py
Executable file
@ -0,0 +1,79 @@
|
||||
#! /usr/bin/python3
|
||||
import sys, os
|
||||
|
||||
################
|
||||
# Helper Funcs #
|
||||
################
|
||||
|
||||
def tokenize(string):
|
||||
tokens = []
|
||||
token = ''
|
||||
whitespace = 0
|
||||
prevWhitespace = 0
|
||||
for char in string:
|
||||
prevWhitespace = whitespace
|
||||
whitespace = char in ' \t\n'
|
||||
if (whitespace):
|
||||
if ((not prevWhitespace) and (token != '')):
|
||||
tokens.append(token)
|
||||
token = ''
|
||||
else:
|
||||
token = token + char
|
||||
return tokens
|
||||
|
||||
#############
|
||||
# Main Code #
|
||||
#############
|
||||
print("Begin parsing state.")
|
||||
|
||||
# Parse Args
|
||||
if len(sys.argv) != 2:
|
||||
sys.exit('Error parseState.py expects 1 arg:\n parseState.py <path_to_checkpoint_dir>')
|
||||
outDir = sys.argv[1]+'/'
|
||||
stateGDBpath = outDir+'intermediate-outputs/stateGDB.txt'
|
||||
if not os.path.exists(stateGDBpath):
|
||||
sys.exit('Error input file '+stateGDBpath+'not found')
|
||||
|
||||
listCSRs = ['hpmcounter','pmpcfg','pmpaddr']
|
||||
singleCSRs = ['mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','mcounteren','sscratch','scause','sepc','stvec','sedeleg','sideleg','scounteren','satp','mstatus']
|
||||
|
||||
# Initialize List CSR files to empty
|
||||
# (because later we'll open them in append mode)
|
||||
for csr in listCSRs:
|
||||
outFileName = 'checkpoint-'+csr.upper()
|
||||
outFile = open(outDir+outFileName, 'w')
|
||||
outFile.close()
|
||||
|
||||
# Initial State for Main Loop
|
||||
currState = 'regFile'
|
||||
regFileIndex = 0
|
||||
outFileName = 'checkpoint-regfile.txt'
|
||||
outFile = open(outDir+outFileName, 'w')
|
||||
|
||||
# Main Loop
|
||||
with open(stateGDBpath, 'r') as stateGDB:
|
||||
for line in stateGDB:
|
||||
line = tokenize(line)
|
||||
name = line[0]
|
||||
val = line[1][2:]
|
||||
if (currState == 'regFile'):
|
||||
if (regFileIndex == 0 and name != 'zero'):
|
||||
print('Whoops! Expected regFile registers to come first, starting with zero')
|
||||
exit(1)
|
||||
outFile.write(val+'\n')
|
||||
regFileIndex += 1
|
||||
if (regFileIndex == 32):
|
||||
outFile.close()
|
||||
currState = 'CSRs'
|
||||
elif (currState == 'CSRs'):
|
||||
if name in singleCSRs:
|
||||
outFileName = 'checkpoint-'+name.upper()
|
||||
outFile = open(outDir+outFileName, 'w')
|
||||
outFile.write(val+'\n')
|
||||
outFile.close()
|
||||
elif name.strip('0123456789') in listCSRs:
|
||||
outFileName = 'checkpoint-'+name.upper().strip('0123456789')
|
||||
outFile = open(outDir+outFileName, 'a')
|
||||
outFile.write(val+'\n')
|
||||
outFile.close()
|
||||
print("Finished parsing state!")
|
@ -2,6 +2,7 @@ onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/reset
|
||||
add wave -noupdate -radix unsigned /testbench/InstrCountW
|
||||
add wave -noupdate /testbench/dut/hart/SATP_REGW
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||
@ -30,25 +31,26 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap
|
||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
|
||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
|
||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||
@ -158,12 +160,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/hart/PCF
|
||||
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/hart/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/hart/PCM
|
||||
add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
|
||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
|
||||
@ -175,41 +177,38 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/genblk1/div/start
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivDoneE
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
||||
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/StartDivideE
|
||||
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/BusyE
|
||||
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/DivDoneM
|
||||
add wave -noupdate /testbench/dut/hart/mdu/genblk1/div/DivInitE
|
||||
add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
||||
@ -232,133 +231,133 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
|
||||
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
@ -383,19 +382,19 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||
add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
|
||||
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
|
||||
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
|
||||
@ -516,8 +515,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 9} {209026335 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {37454355 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
configure wave -justifyvalue left
|
||||
@ -532,4 +531,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {209183151 ns} {209183343 ns}
|
||||
WaveRestoreZoom {37454022 ns} {37455158 ns}
|
||||
|
24
wally-pipelined/regression/old/qrun.do
Normal file
24
wally-pipelined/regression/old/qrun.do
Normal file
@ -0,0 +1,24 @@
|
||||
# qrun.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-pipelined-batch.do <config> <testcases>
|
||||
# Example: do wally-pipelined-batch.do rv32 imperas-32i
|
||||
|
||||
# Use this wally-pipelined-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined-batch.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined-batch.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
qrun -clean
|
||||
qrun +incdir+../config/rv32ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583 -optimize -snapshot wally +notimingchecks +nospecify
|
||||
qrun -simulate -snapshot wally
|
||||
qrun -simulate -snapshot wally
|
||||
|
215
wally-pipelined/regression/old/qrun.log
Normal file
215
wally-pipelined/regression/old/qrun.log
Normal file
@ -0,0 +1,215 @@
|
||||
QuestaSim-64 qrun 2021.2_1 Utility 2021.05 May 15 2021
|
||||
Start time: 21:17:08 on Oct 09,2021
|
||||
qrun -simulate -snapshot wally
|
||||
# vsim -lib qrun.out/work -c -do "run -all; quit -f" -statslog qrun.out/stats_log wally -appendlog -l qrun.log
|
||||
# Start time: 21:17:09 on Oct 09,2021
|
||||
# // Questa Sim-64
|
||||
# // Version 2021.2_1 linux_x86_64 May 15 2021
|
||||
# //
|
||||
# // Copyright 1991-2021 Mentor Graphics Corporation
|
||||
# // All Rights Reserved.
|
||||
# //
|
||||
# // QuestaSim and its associated documentation contain trade
|
||||
# // secrets and commercial or financial information that are the property of
|
||||
# // Mentor Graphics Corporation and are privileged, confidential,
|
||||
# // and exempt from disclosure under the Freedom of Information Act,
|
||||
# // 5 U.S.C. Section 552. Furthermore, this information
|
||||
# // is prohibited from disclosure under the Trade Secrets Act,
|
||||
# // 18 U.S.C. Section 1905.
|
||||
# //
|
||||
# Loading sv_std.std
|
||||
# Loading work.cla_sub52(fast)
|
||||
# Loading work.convert_inputs(fast)
|
||||
# Loading work.convert_inputs_div(fast)
|
||||
# Loading work.decoder(fast)
|
||||
# Loading work.faddcvt(fast)
|
||||
# Loading work.floprc(fast)
|
||||
# Loading work.fpudivsqrtrecur(fast)
|
||||
# Loading work.intdiv(fast)
|
||||
# Loading work.lz52(fast)
|
||||
# Loading work.qsel(fast)
|
||||
# Loading work.ahbliteState(fast)
|
||||
# Loading work.testbench_sv_unit(fast)
|
||||
# Loading work.testbench(fast)
|
||||
# Loading work.regfile(fast)
|
||||
# Loading work.csrn(fast)
|
||||
# Loading work.instrTrackerTB(fast)
|
||||
# Loading work.instrNameDecTB(fast)
|
||||
# Loading work.copyShadow(fast)
|
||||
# Loading work.tlbcamline(fast)
|
||||
# Loading work.pmpadrdec(fast)
|
||||
# Loading work.cacheway(fast)
|
||||
# Loading work.cacheway(fast__1)
|
||||
# run -all
|
||||
# ** Warning: Multiple Instruction Cache ways not yet implemented
|
||||
# Time: 0 ns Scope: testbench.riscvassertions File: ../testbench/testbench.sv Line: 327
|
||||
# ** Error: Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF
|
||||
# Time: 0 ns Scope: testbench.riscvassertions File: ../testbench/testbench.sv Line: 330
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ADD-01.elf.memfile
|
||||
# rv32i/I-ADD-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ADDI-01.elf.memfile
|
||||
# rv32i/I-ADDI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-AND-01.elf.memfile
|
||||
# rv32i/I-AND-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ANDI-01.elf.memfile
|
||||
# rv32i/I-ANDI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-AUIPC-01.elf.memfile
|
||||
# rv32i/I-AUIPC-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BEQ-01.elf.memfile
|
||||
# rv32i/I-BEQ-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BGE-01.elf.memfile
|
||||
# rv32i/I-BGE-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BGEU-01.elf.memfile
|
||||
# rv32i/I-BGEU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BLT-01.elf.memfile
|
||||
# rv32i/I-BLT-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BLTU-01.elf.memfile
|
||||
# rv32i/I-BLTU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BNE-01.elf.memfile
|
||||
# rv32i/I-BNE-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-DELAY_SLOTS-01.elf.memfile
|
||||
# rv32i/I-DELAY_SLOTS-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-EBREAK-01.elf.memfile
|
||||
# rv32i/I-EBREAK-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ECALL-01.elf.memfile
|
||||
# rv32i/I-ECALL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ENDIANESS-01.elf.memfile
|
||||
# rv32i/I-ENDIANESS-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-IO-01.elf.memfile
|
||||
# rv32i/I-IO-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-JAL-01.elf.memfile
|
||||
# rv32i/I-JAL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-JALR-01.elf.memfile
|
||||
# rv32i/I-JALR-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LB-01.elf.memfile
|
||||
# 790020 Warning: access to memory address 0
|
||||
#
|
||||
# rv32i/I-LB-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LBU-01.elf.memfile
|
||||
# rv32i/I-LBU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LH-01.elf.memfile
|
||||
# rv32i/I-LH-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LHU-01.elf.memfile
|
||||
# rv32i/I-LHU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LUI-01.elf.memfile
|
||||
# rv32i/I-LUI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LW-01.elf.memfile
|
||||
# rv32i/I-LW-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-MISALIGN_LDST-01.elf.memfile
|
||||
# rv32i/I-MISALIGN_LDST-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-NOP-01.elf.memfile
|
||||
# rv32i/I-NOP-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-OR-01.elf.memfile
|
||||
# rv32i/I-OR-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ORI-01.elf.memfile
|
||||
# rv32i/I-ORI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-RF_size-01.elf.memfile
|
||||
# rv32i/I-RF_size-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-RF_width-01.elf.memfile
|
||||
# rv32i/I-RF_width-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-RF_x0-01.elf.memfile
|
||||
# rv32i/I-RF_x0-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SB-01.elf.memfile
|
||||
# 1233020 Warning: access to memory address 0
|
||||
#
|
||||
# rv32i/I-SB-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SH-01.elf.memfile
|
||||
# rv32i/I-SH-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLL-01.elf.memfile
|
||||
# rv32i/I-SLL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLLI-01.elf.memfile
|
||||
# rv32i/I-SLLI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLT-01.elf.memfile
|
||||
# rv32i/I-SLT-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLTI-01.elf.memfile
|
||||
# rv32i/I-SLTI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLTIU-01.elf.memfile
|
||||
# rv32i/I-SLTIU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLTU-01.elf.memfile
|
||||
# rv32i/I-SLTU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRA-01.elf.memfile
|
||||
# rv32i/I-SRA-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRAI-01.elf.memfile
|
||||
# rv32i/I-SRAI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRL-01.elf.memfile
|
||||
# rv32i/I-SRL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRLI-01.elf.memfile
|
||||
# rv32i/I-SRLI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SUB-01.elf.memfile
|
||||
# rv32i/I-SUB-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SW-01.elf.memfile
|
||||
# rv32i/I-SW-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-XOR-01.elf.memfile
|
||||
# rv32i/I-XOR-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-XORI-01.elf.memfile
|
||||
# rv32i/I-XORI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ADD.elf.memfile
|
||||
# rv32i/WALLY-ADD succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SUB.elf.memfile
|
||||
# rv32i/WALLY-SUB succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ADDI.elf.memfile
|
||||
# rv32i/WALLY-ADDI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ANDI.elf.memfile
|
||||
# rv32i/WALLY-ANDI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ORI.elf.memfile
|
||||
# rv32i/WALLY-ORI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-XORI.elf.memfile
|
||||
# rv32i/WALLY-XORI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SLTI.elf.memfile
|
||||
# rv32i/WALLY-SLTI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SLTIU.elf.memfile
|
||||
# rv32i/WALLY-SLTIU succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SLLI.elf.memfile
|
||||
# rv32i/WALLY-SLLI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SRLI.elf.memfile
|
||||
# rv32i/WALLY-SRLI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SRAI.elf.memfile
|
||||
# rv32i/WALLY-SRAI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-LOAD.elf.memfile
|
||||
# rv32i/WALLY-LOAD succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SUB.elf.memfile
|
||||
# rv32i/WALLY-SUB succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-STORE.elf.memfile
|
||||
# rv32i/WALLY-STORE succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-JAL.elf.memfile
|
||||
# rv32i/WALLY-JAL succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-JALR.elf.memfile
|
||||
# rv32i/WALLY-JALR succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BEQ.elf.memfile
|
||||
# 2846200 Warning: access to memory address 0
|
||||
#
|
||||
# rv32i/WALLY-BEQ succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BNE.elf.memfile
|
||||
# rv32i/WALLY-BNE succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BLTU.elf.memfile
|
||||
# rv32i/WALLY-BLTU succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BLT.elf.memfile
|
||||
# rv32i/WALLY-BLT succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BGE.elf.memfile
|
||||
# rv32i/WALLY-BGE succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BGEU.elf.memfile
|
||||
# rv32i/WALLY-BGEU succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRW.elf.memfile
|
||||
# rv32i/WALLY-CSRRW succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRS.elf.memfile
|
||||
# rv32i/WALLY-CSRRS succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRC.elf.memfile
|
||||
# rv32i/WALLY-CSRRC succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRWI.elf.memfile
|
||||
# rv32i/WALLY-CSRRWI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRSI.elf.memfile
|
||||
# rv32i/WALLY-CSRRSI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRCI.elf.memfile
|
||||
# rv32i/WALLY-CSRRCI succeeded. Brilliant!!!
|
||||
# SUCCESS! All tests ran without failures.
|
||||
# ** Note: $stop : ../testbench/testbench.sv(244)
|
||||
# Time: 4170295 ns Iteration: 0 Instance: /testbench
|
||||
# Break at ../testbench/testbench.sv line 244
|
||||
# Stopped at ../testbench/testbench.sv line 244
|
||||
# quit -f
|
||||
# End time: 21:17:54 on Oct 09,2021, Elapsed time: 0:00:45
|
||||
# Errors: 1, Warnings: 1
|
||||
# *** Summary *********************************************
|
||||
# qrun: Errors: 0, Warnings: 0
|
||||
# vsim: Errors: 1, Warnings: 1
|
||||
# Totals: Errors: 1, Warnings: 1
|
6
wally-pipelined/regression/old/qrun.out/history
Normal file
6
wally-pipelined/regression/old/qrun.out/history
Normal file
@ -0,0 +1,6 @@
|
||||
- Entry: 1
|
||||
Time: Sat Oct 9 21:16:56 2021
|
||||
Command: /cad/mentor/questa_sim-2021.2_1/questasim/linux_x86_64/qrun +incdir+../config/rv32ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/function_radix.sv ../testbench/common/instrNameDecTB.sv ../testbench/common/instrTrackerTB.sv ../testbench/common/logging.sv ../src/cache/cachereplacementpolicy.sv ../src/cache/cacheway.sv ../src/cache/dcache.sv ../src/cache/dcachefsm.sv ../src/cache/icache.sv ../src/cache/icachefsm.sv ../src/cache/sram1rw.sv ../src/ebu/ahblite.sv ../src/ebu/amoalu.sv ../src/fpu/adder.sv ../src/fpu/cla12.sv ../src/fpu/cla52.sv ../src/fpu/cla64.sv ../src/fpu/convert_inputs.sv ../src/fpu/convert_inputs_div.sv ../src/fpu/cvtfp.sv ../src/fpu/divconv.sv ../src/fpu/exception.sv ../src/fpu/exception_div.sv ../src/fpu/faddcvt.sv ../src/fpu/fclassify.sv ../src/fpu/fcmp.sv ../src/fpu/fctrl.sv ../src/fpu/fcvt.sv ../src/fpu/fhazard.sv ../src/fpu/fma.sv ../src/fpu/fpdiv.sv ../src/fpu/fpu.sv ../src/fpu/fpudivsqrtrecur.sv ../src/fpu/fpudivsqrtrecurcore.sv ../src/fpu/fregfile.sv ../src/fpu/fsgn.sv ../src/fpu/fsm.sv ../src/fpu/lzd_denorm.sv ../src/fpu/rounder_denorm.sv ../src/fpu/rounder_div.sv ../src/fpu/sbtm_a0.sv ../src/fpu/sbtm_a1.sv ../src/fpu/sbtm_a2.sv ../src/fpu/sbtm_a3.sv ../src/fpu/sbtm_div.sv ../src/fpu/sbtm_sqrt.sv ../src/fpu/shifter_denorm.sv ../src/fpu/unpacking.sv ../src/generic/adder.sv ../src/generic/clockgater.sv ../src/generic/flop.sv ../src/generic/lzd.sv ../src/generic/mux.sv ../src/generic/neg.sv ../src/generic/onehotdecoder.sv ../src/generic/or_rows.sv ../src/generic/shift.sv ../src/hazard/hazard.sv ../src/ieu/alu.sv ../src/ieu/controller.sv ../src/ieu/datapath.sv ../src/ieu/extend.sv ../src/ieu/forward.sv ../src/ieu/ieu.sv ../src/ieu/regfile.sv ../src/ieu/shifter.sv ../src/ifu/BTBPredictor.sv ../src/ifu/RAsPredictor.sv ../src/ifu/SRAM2P1R1W.sv ../src/ifu/bpred.sv ../src/ifu/decompress.sv ../src/ifu/globalHistoryPredictor.sv ../src/ifu/gsharePredictor.sv ../src/ifu/ifu.sv ../src/ifu/localHistoryPredictor.sv ../src/ifu/satCounter2.sv ../src/ifu/twoBitPredictor.sv ../src/lsu/lrsc.sv ../src/lsu/lsu.sv ../src/lsu/lsuArb.sv ../src/lsu/subwordread.sv ../src/mmu/adrdec.sv ../src/mmu/adrdecs.sv ../src/mmu/decoder.sv ../src/mmu/hptw.sv ../src/mmu/mmu.sv ../src/mmu/pmachecker.sv ../src/mmu/pmpadrdec.sv ../src/mmu/pmpchecker.sv ../src/mmu/priorityonehot.sv ../src/mmu/prioritythermometer.sv ../src/mmu/tlb.sv ../src/mmu/tlbcam.sv ../src/mmu/tlbcamline.sv ../src/mmu/tlbcontrol.sv ../src/mmu/tlblru.sv ../src/mmu/tlbmixer.sv ../src/mmu/tlbram.sv ../src/mmu/tlbramline.sv ../src/muldiv/div.sv ../src/muldiv/intdivrestoring.sv ../src/muldiv/intdivrestoringstep.sv ../src/muldiv/mul.sv ../src/muldiv/muldiv.sv ../src/privileged/csr.sv ../src/privileged/csrc.sv ../src/privileged/csri.sv ../src/privileged/csrm.sv ../src/privileged/csrn.sv ../src/privileged/csrs.sv ../src/privileged/csrsr.sv ../src/privileged/csru.sv ../src/privileged/privdec.sv ../src/privileged/privileged.sv ../src/privileged/trap.sv ../src/uncore/clint.sv ../src/uncore/dtim.sv ../src/uncore/gpio.sv ../src/uncore/plic.sv ../src/uncore/subwordwrite.sv ../src/uncore/uart.sv ../src/uncore/uartPC16550D.sv ../src/uncore/uncore.sv ../src/wally/wallypipelinedhart.sv ../src/wally/wallypipelinedsoc.sv -suppress 2583 -optimize -snapshot wally +notimingchecks +nospecify
|
||||
- Entry: 2
|
||||
Time: Sat Oct 9 21:17:08 2021
|
||||
Command: /cad/mentor/questa_sim-2021.2_1/questasim/linux_x86_64/qrun -simulate -snapshot wally
|
1
wally-pipelined/regression/old/qrun.out/history.cnt
Normal file
1
wally-pipelined/regression/old/qrun.out/history.cnt
Normal file
@ -0,0 +1 @@
|
||||
2
|
BIN
wally-pipelined/regression/old/qrun.out/sessions/qrun.out$work
Normal file
BIN
wally-pipelined/regression/old/qrun.out/sessions/qrun.out$work
Normal file
Binary file not shown.
2
wally-pipelined/regression/old/qrun.out/stats_log
Normal file
2
wally-pipelined/regression/old/qrun.out/stats_log
Normal file
@ -0,0 +1,2 @@
|
||||
qrun: Errors: 0, Warnings: 0
|
||||
vsim: Errors: 1, Warnings: 1
|
1
wally-pipelined/regression/old/qrun.out/top_dus
Normal file
1
wally-pipelined/regression/old/qrun.out/top_dus
Normal file
@ -0,0 +1 @@
|
||||
/mnt/scratch/harris_scratch/riscv-wally/wally-pipelined/regression/qrun.out/work 0 compiled
|
1
wally-pipelined/regression/old/qrun.out/version
Normal file
1
wally-pipelined/regression/old/qrun.out/version
Normal file
@ -0,0 +1 @@
|
||||
qrun 0.5
|
1
wally-pipelined/regression/old/sim-fp64
Executable file
1
wally-pipelined/regression/old/sim-fp64
Executable file
@ -0,0 +1 @@
|
||||
vsim -do wally-fp64.do
|
3
wally-pipelined/regression/old/sim-fp64-batch
Executable file
3
wally-pipelined/regression/old/sim-fp64-batch
Executable file
@ -0,0 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-fp64-batch.do ../config/rv64icfd rv64icfd
|
||||
!
|
3
wally-pipelined/regression/old/sim-wally-batch-rv32ic
Executable file
3
wally-pipelined/regression/old/sim-wally-batch-rv32ic
Executable file
@ -0,0 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-pipelined-batch.do rv32ic imperas-32i
|
||||
!
|
@ -31,27 +31,7 @@ configs = [
|
||||
TestCase(
|
||||
name="buildroot",
|
||||
cmd="vsim -do wally-buildroot-batch.do -c > {}",
|
||||
grepstr="8900000 instructions"
|
||||
),
|
||||
TestCase(
|
||||
name="arch64",
|
||||
cmd="vsim > {} -c <<!\ndo wally-arch.do ../config/rv64ic rv64ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
),
|
||||
TestCase(
|
||||
name="arch32",
|
||||
cmd="vsim > {} -c <<!\ndo wally-arch.do ../config/rv32ic rv32ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
),
|
||||
TestCase(
|
||||
name="rv32ic",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do ../config/rv32ic rv32ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
),
|
||||
TestCase(
|
||||
name="rv64ic",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do ../config/rv64ic rv64ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
grepstr="8500000 instructions"
|
||||
),
|
||||
TestCase(
|
||||
name="lints",
|
||||
@ -60,6 +40,23 @@ configs = [
|
||||
),
|
||||
]
|
||||
|
||||
tests64 = ["arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"]
|
||||
for test in tests64:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
|
||||
for test in tests32:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32g "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
|
||||
import os
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
||||
@ -70,7 +67,7 @@ def search_log_for_text(text, logfile):
|
||||
|
||||
def run_test_case(config):
|
||||
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
|
||||
logname = "regression_logs/wally_"+config.name+".log"
|
||||
logname = "logs/wally_"+config.name+".log"
|
||||
cmd = config.cmd.format(logname)
|
||||
print(cmd)
|
||||
os.system(cmd)
|
||||
@ -85,13 +82,13 @@ def run_test_case(config):
|
||||
def main():
|
||||
"""Run the tests and count the failures"""
|
||||
# Scale the number of concurrent processes to the number of test cases, but
|
||||
# max out at 12 concurrent processes to not overwhelm the system
|
||||
# max out at a limited number of concurrent processes to not overwhelm the system
|
||||
TIMEOUT_DUR = 1800 # seconds
|
||||
try:
|
||||
os.mkdir("regression_logs")
|
||||
os.mkdir("logs")
|
||||
except:
|
||||
pass
|
||||
with Pool(processes=min(len(configs),12)) as pool:
|
||||
with Pool(processes=min(len(configs),25)) as pool:
|
||||
num_fail = 0
|
||||
results = {}
|
||||
for config in configs:
|
||||
|
@ -1,3 +0,0 @@
|
||||
#!/bin/sh
|
||||
vsim -do $1
|
||||
|
@ -1 +1,2 @@
|
||||
vsim -do wally-pipelined.do
|
||||
vsim -do "do wally-pipelined.do rv32g arch32m"
|
||||
|
||||
|
@ -1,3 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-pipelined-batch.do ../config/rv64ic rv64ic
|
||||
do wally-pipelined-batch.do rv64g arch64m
|
||||
!
|
||||
|
@ -1,3 +0,0 @@
|
||||
vsim -c <<!
|
||||
do wally-pipelined-batch.do ../config/rv32ic rv32ic
|
||||
!
|
@ -1,22 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
int main() {
|
||||
|
||||
uint64_t N;
|
||||
uint64_t D;
|
||||
uint64_t Q;
|
||||
|
||||
D = 0xdf7f3844121bcc23;
|
||||
N = 0x10fd3dedadea5195;
|
||||
Q = N/D;
|
||||
|
||||
printf("N = %" PRIx64 "\n", N);
|
||||
printf("D = %" PRIx64 "\n", D);
|
||||
printf("Q = %" PRIx64 "\n", Q);
|
||||
printf("R = %" PRIx64 "\n", N%D);
|
||||
|
||||
|
||||
|
||||
}
|
@ -7,6 +7,9 @@
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-pipelined-batch.do <config> <testcases>
|
||||
# Example: do wally-pipelined-batch.do rv32ic imperas-32i
|
||||
|
||||
# Use this wally-pipelined-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined-batch.do
|
||||
@ -17,10 +20,10 @@
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work_$2] {
|
||||
vdel -lib work_$2 -all
|
||||
if [file exists work_${1}_${2}] {
|
||||
vdel -lib work_${1}_${2} -all
|
||||
}
|
||||
vlib work_$2
|
||||
vlib work_${1}_${2}
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
@ -29,15 +32,12 @@ vlib work_$2
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
|
||||
switch $argc {
|
||||
0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
}
|
||||
vlog -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt work_$2.testbench -work work_$2 -o workopt_$2
|
||||
vsim -lib work_$2 workopt_$2
|
||||
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt
|
||||
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
|
||||
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
|
||||
#vsim -coverage -lib work_$2 workopt_$2
|
||||
|
@ -7,6 +7,8 @@
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
@ -29,13 +31,14 @@ vlib work
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
switch $argc {
|
||||
0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
}
|
||||
#switch $argc {
|
||||
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
#}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt +acc work.testbench -o workopt
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
|
||||
vopt +acc work.testbench -G TEST=$2 -o workopt
|
||||
vsim workopt
|
||||
|
||||
view wave
|
||||
@ -43,8 +46,9 @@ view wave
|
||||
do ./wave-dos/peripheral-waves.do
|
||||
|
||||
-- Run the Simulation
|
||||
#run 5000
|
||||
#run 3600
|
||||
run -all
|
||||
#quit
|
||||
noview ../testbench/testbench-imperas.sv
|
||||
#noview ../testbench/testbench-imperas.sv
|
||||
noview ../testbench/testbench.sv
|
||||
view wave
|
||||
|
23
wally-pipelined/regression/wave-dos/generic.do
Normal file
23
wally-pipelined/regression/wave-dos/generic.do
Normal file
@ -0,0 +1,23 @@
|
||||
# default-waves.do
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {300 ps}
|
||||
configure wave -namecolwidth 350
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
@ -35,6 +35,11 @@ add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
|
||||
add wave /testbench/dut/hart/mdu/genblk1/div/DivStartE
|
||||
add wave /testbench/dut/hart/mdu/DivBusyE
|
||||
add wave -hex /testbench/dut/hart/mdu/genblk1/div/RemM
|
||||
add wave -hex /testbench/dut/hart/mdu/genblk1/div/QuotM
|
||||
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCM
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrM
|
||||
@ -48,9 +53,9 @@ add wave -hex /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||
add wave -hex /testbench/dut/hart/ebu/ReadDataM
|
||||
add wave -divider
|
||||
add wave -hex /testbench/PCW
|
||||
add wave -hex /testbench/InstrW
|
||||
#add wave -hex /testbench/InstrW
|
||||
add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
|
||||
add wave /testbench/InstrWName
|
||||
#add wave /testbench/InstrWName
|
||||
add wave -hex /testbench/dut/hart/ReadDataW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/RegWriteW
|
||||
|
@ -114,463 +114,426 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/h
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PrivilegedChangePCM
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/c/RegWriteD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/RdD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/Rs1D
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/Rs2D
|
||||
add wave -noupdate -group RegFile -expand /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rf
|
||||
add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/a1
|
||||
add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/a2
|
||||
add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/a3
|
||||
add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rd1
|
||||
add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rd2
|
||||
add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/we3
|
||||
add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/wd3
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ALUResultW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ReadDataW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultW
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/a
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/b
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/alucontrol
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/result
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/flags
|
||||
add wave -noupdate -expand -group alu -divider internals
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/overflow
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/carry
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/zero
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/neg
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/lt
|
||||
add wave -noupdate -expand -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/ltu
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1D
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs2D
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1E
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs2E
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RdE
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RdM
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RdW
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/MemReadE
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RegWriteM
|
||||
add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RegWriteW
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/hart/ieu/fw/ForwardAE
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/hart/ieu/fw/ForwardBE
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/hart/ieu/fw/LoadStallD
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/WriteDataE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/SrcBE
|
||||
add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCF
|
||||
add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCM
|
||||
add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/InstrD
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/SrcAE
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/SrcBE
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/Funct3E
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/MulDivE
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/W64E
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/StallM
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/StallW
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/FlushM
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/FlushW
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/MulDivResultW
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/genblk1/div/start
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/DivDoneE
|
||||
add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/DivBusyE
|
||||
add wave -noupdate -group divider /testbench/dut/wallypipelinedsoc/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
|
||||
add wave -noupdate -group divider /testbench/dut/wallypipelinedsoc/hart/mdu/genblk1/div/N
|
||||
add wave -noupdate -group divider /testbench/dut/wallypipelinedsoc/hart/mdu/genblk1/div/D
|
||||
add wave -noupdate -group divider /testbench/dut/wallypipelinedsoc/hart/mdu/genblk1/div/Q
|
||||
add wave -noupdate -group divider /testbench/dut/wallypipelinedsoc/hart/mdu/genblk1/div/rem0
|
||||
add wave -noupdate -group icache -color Gold /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/BasePAdrF
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/WayHit
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/VictimWay
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/PCNextIndexF
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/BasePAdrF
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/SavePC
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/UnalignedSelect
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/InstrPAdrF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/InstrInF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/FetchCount
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/wallypipelinedsoc/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/hart/ebu/AtomicMaskedM
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/hart/ebu/InstrReadF
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/hart/ebu/MemSizeM
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HRESETn
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HRDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HREADY
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HRESP
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HADDR
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HWDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HWRITE
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HSIZE
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HBURST
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HMASTLOCK
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HADDRD
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HSIZED
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HWRITED
|
||||
add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/StallW
|
||||
add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/wallypipelinedsoc/hart/lsu/arbiter/SelPTW
|
||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/WalkerPageFaultM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SRAMWordEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/FlushAdrFlag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/FetchCount
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/FetchCountFlag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/AHBRead
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/AHBWrite
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/AHBAck
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/HRDATA
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/HWDATA
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/PCF
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/TranslationPAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/HPTWReadPTE
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/PTE
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/ITLBMissF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/DTLBMissM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/DTLBWriteM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/WalkerStorePageFaultM
|
||||
add wave -noupdate -group csr /testbench/dut/wallypipelinedsoc/hart/priv/csr/MIP_REGW
|
||||
add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/hart/ifu/immu/TLBWrite
|
||||
add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/hart/ifu/immu/PhysicalAddress
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VAdr
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HCLK
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HSELPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HADDR
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HWRITE
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HREADY
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HTRANS
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HWDATA
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HREADPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HRESPPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HREADYPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/ExtIntM
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HCLK
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HSELGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HADDR
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HWDATA
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HWRITE
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HREADY
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HTRANS
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HREADGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HRESPGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HREADYGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HCLK
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HSELCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HADDR
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HWRITE
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HWDATA
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HREADY
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HTRANS
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HREADCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HRESPCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HREADYCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/TimerIntM
|
||||
add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/SwIntM
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HCLK
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HRESETn
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HSELUART
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HADDR
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWRITE
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HREADUART
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HRESPUART
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HREADYUART
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/RIb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HCLK
|
||||
add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HSELUART
|
||||
add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HADDR
|
||||
add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWRITE
|
||||
add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {AHBLite FSM} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/CurrState
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HCLK
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/CLKGate
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/SDCCLKIn
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/SDCCLK
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {cmd fsm} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {dat fsm} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {clk fsm} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/SDCDat
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/SDCCmd
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/SDCCLK
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE
|
||||
add wave -noupdate -expand -group SDC -group registers /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/CLKDiv
|
||||
add wave -noupdate -expand -group SDC -group registers /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/Command
|
||||
add wave -noupdate -expand -group SDC -group registers -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/Status
|
||||
add wave -noupdate -expand -group SDC -group registers /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/Address
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} -color Aquamarine /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HSELSDC
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HADDR
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HADDRDelay
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HWRITE
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADY
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HTRANS
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HWDATA
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADSDC
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HRESPSDC
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} -color Goldenrod /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADYSDC
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/InitTrans
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/o_ERROR_CODE_Q
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/o_DATA_VALID
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/ReadData
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/WordCount
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADSDC
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/o_READY_FOR_READ
|
||||
add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HADDR
|
||||
add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/A
|
||||
add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HWADDR
|
||||
add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HSELTim
|
||||
add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HREADYTim
|
||||
add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HRESPTim
|
||||
add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/initTrans
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/SDCDataValid
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_instruction_control_bits
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/w_error_result
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/o_RX_SIPO48_EN
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_RESPONSE_CONTENT
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_MASK
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_ANS
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_command_head
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_command_content
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/r_DAT3_CRC16
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/r_DAT2_CRC16
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/r_DAT1_CRC16
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/r_DAT0_CRC16
|
||||
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_DATA_CRC16_GOOD
|
||||
add wave -noupdate -radix binary /testbench/sdcard/dataState
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
|
||||
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
|
||||
add wave -noupdate -group alu -divider internals
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2E
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdE
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdM
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdW
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/MemReadE
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteM
|
||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteW
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardAE
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardBE
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/LoadStallD
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/WriteDataE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
|
||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/genblk1/div/start
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivDoneM
|
||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
||||
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
|
||||
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushAdrFlag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/FetchCountFlag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HCLK
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESETn
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HSELUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HADDR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWRITE
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESPUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADYUART
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK
|
||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
|
||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -color Gold /testbench/dut/hart/lsu/dcache/subwordread/offset0
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
|
||||
add wave -noupdate /testbench/dut/hart/ExceptionM
|
||||
add wave -noupdate /testbench/dut/hart/PendingInterruptM
|
||||
add wave -noupdate /testbench/dut/hart/TrapM
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCPF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/PCF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/immu/Translate
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/StallF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 6} {598422 ns} 0} {{Cursor 3} {603500 ns} 1}
|
||||
quietly wave cursor active 1
|
||||
|
@ -1,9 +1,26 @@
|
||||
// This module takes as inputs two operands (op1 and op2)
|
||||
// the operation type (op_type) and the result precision (P).
|
||||
// Based on the operation and precision , it conditionally
|
||||
// converts single precision values to double precision values
|
||||
// and modifies the sign of op1. The converted operands are Float1
|
||||
// and Float2.
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Floating point divider/square root top unit (Goldschmidt)
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module convert_inputs(
|
||||
input [63:0] op1, // 1st input operand (A)
|
||||
|
@ -23,9 +23,10 @@ module exception_div (
|
||||
logic BNaN; // '1' if B is a not-a-number
|
||||
logic ASNaN; // '1' if A is a signalling not-a-number
|
||||
logic BSNaN; // '1' if B is a signalling not-a-number
|
||||
logic ZQNaN; // '1' if result Z is a quiet NaN
|
||||
logic ZSNaN; // '1' if result Z is a quiet NaN
|
||||
logic ZInf; // '1' if result Z is an infnity
|
||||
logic Zero; // '1' if result is zero
|
||||
logic Zero; // '1' if result is zero
|
||||
logic NegSqrt; // '1' if sqrt and operand is negative
|
||||
|
||||
//***take this module out and add more registers or just recalculate it all
|
||||
// Determine if mantissas are all zeros
|
||||
@ -48,32 +49,34 @@ module exception_div (
|
||||
assign AZero = AzeroE & AzeroM;
|
||||
assign BZero = BzeroE & BzeroE;
|
||||
|
||||
// Is NaN if operand is negative and its a sqrt
|
||||
assign NegSqrt = (A[63] & op_type & ~AZero);
|
||||
|
||||
// An "Invalid Operation" exception occurs if (A or B is a signalling NaN)
|
||||
// or (A and B are both Infinite)
|
||||
assign Invalid = ASNaN | BSNaN | (((AInf & BInf) | (AZero & BZero))&~op_type) |
|
||||
(A[63] & op_type);
|
||||
|
||||
NegSqrt;
|
||||
|
||||
// The result is a quiet NaN if (an "Invalid Operation" exception occurs)
|
||||
// or (A is a NaN) or (B is a NaN).
|
||||
assign ZQNaN = Invalid | ANaN | BNaN;
|
||||
assign ZSNaN = Invalid | ANaN | BNaN;
|
||||
|
||||
// The result is zero
|
||||
assign Zero = (AZero | BInf)&~op_type | AZero&op_type;
|
||||
|
||||
// The result is +Inf if ((A is Inf) or (B is 0)) and (the
|
||||
// result is not a quiet NaN).
|
||||
assign ZInf = (AInf | BZero)&~ZQNaN&~op_type | AInf&op_type&~ZQNaN;
|
||||
assign ZInf = (AInf | BZero)&~ZSNaN&~op_type | AInf&op_type&~ZSNaN;
|
||||
|
||||
// Set the type of the result as follows:
|
||||
// Ztype Result
|
||||
// 000 Normal
|
||||
// 001 Quiet NaN
|
||||
// 010 Infinity
|
||||
// 011 Zero
|
||||
// 110 DivZero
|
||||
assign Ztype[0] = ZQNaN | Zero;
|
||||
assign Ztype[1] = ZInf | Zero;
|
||||
assign Ztype[2] = BZero&~op_type;
|
||||
|
||||
// 110 Div by 0
|
||||
// 111 SNaN
|
||||
assign Ztype[2] = (ZSNaN);
|
||||
assign Ztype[1] = (ZSNaN) | (Zero) | (ZInf);
|
||||
assign Ztype[0] = (ZSNaN) | (Zero);
|
||||
|
||||
endmodule // exception
|
||||
|
@ -23,7 +23,7 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
// `include "../../../config/rv64icfd/wally-config.vh"
|
||||
// `include "../../../config/rv64icfd/wally-config.vh"
|
||||
|
||||
module fma(
|
||||
input logic clk,
|
||||
@ -45,7 +45,6 @@ module fma(
|
||||
input logic XSNaNM, YSNaNM, ZSNaNM, // is signaling NaN
|
||||
input logic XZeroM, YZeroM, ZZeroM, // is zero - memory stage
|
||||
input logic XInfM, YInfM, ZInfM, // is infinity
|
||||
input logic [10:0] BiasE, // bias (max exponent/2) ***parameterize in unpacking unit
|
||||
output logic [`FLEN-1:0] FMAResM, // FMA result
|
||||
output logic [4:0] FMAFlgM); // FMA flags
|
||||
|
||||
@ -70,7 +69,7 @@ module fma(
|
||||
logic [8:0] NormCntE, NormCntM;
|
||||
|
||||
fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.BiasE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
|
||||
.XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
|
||||
.FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE,
|
||||
.ProdExpE, .AddendStickyE, .KillProdE);
|
||||
|
||||
@ -96,7 +95,6 @@ module fma1(
|
||||
input logic [`NF:0] XManE, YManE, ZManE, // fractions in U(0.NF) format
|
||||
input logic XDenormE, YDenormE, ZDenormE, // is the input denormal
|
||||
input logic XZeroE, YZeroE, ZZeroE, // is the input zero
|
||||
input logic [`NE-1:0] BiasE, // bias (max exponent/2)
|
||||
input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
|
||||
input logic FmtE, // precision 1 = double 0 = single
|
||||
output logic [`NE+1:0] ProdExpE, // X exponent + Y exponent - bias in B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
|
||||
@ -111,25 +109,26 @@ module fma1(
|
||||
);
|
||||
|
||||
logic [`NE-1:0] Denorm; // value of a denormaized number based on precision
|
||||
logic [`NE-1:0] XExpVal, YExpVal; // Exponent value after taking into account denormals
|
||||
logic [2*`NF+1:0] ProdManE; // 1.X frac * 1.Y frac in U(2.2Nf) format
|
||||
logic [3*`NF+5:0] AlignedAddendE; // Z aligned for addition in U(NF+5.2NF+1)
|
||||
logic [3*`NF+6:0] AlignedAddendInv; // aligned addend possibly inverted
|
||||
logic [2*`NF+1:0] ProdManKilled; // the product's mantissa possibly killed
|
||||
logic [3*`NF+6:0] NegProdManKilled; // a negated ProdManKilled
|
||||
logic [8:0] PNormCnt, NNormCnt; // the positive and nagitive LOA results
|
||||
logic [3*`NF+6:0] PreSum, NegPreSum; // positive and negitve versions of the sum
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Calculate the product
|
||||
// - When multipliying two fp numbers, add the exponents
|
||||
// - Subtract the bias (XExp + YExp has two biases, one from each exponent)
|
||||
// - If the product is zero then kill the exponent - this is a problem
|
||||
// - If the product is zero then kill the exponent
|
||||
// - Multiply the mantissas
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// denormalized numbers have diffrent values depending on which precison it is.
|
||||
// double - 1
|
||||
// single - 1024-128+1 = 897
|
||||
assign Denorm = FmtE ? 1 : 897;
|
||||
assign XExpVal = XDenormE ? Denorm : XExpE;
|
||||
assign YExpVal = YDenormE ? Denorm : YExpE;
|
||||
// take into account if the product is zero, the product's exponent does not compute properly if X or Y is zero
|
||||
assign ProdExpE = (XExpVal + YExpVal - BiasE)&{`NE+2{~(XZeroE|YZeroE)}};
|
||||
|
||||
// calculate the product's exponent
|
||||
expadd expadd(.FmtE, .XExpE, .YExpE, .XZeroE, .YZeroE, .XDenormE, .YDenormE,
|
||||
.Denorm, .ProdExpE);
|
||||
|
||||
// multiplication of the mantissa's
|
||||
mult mult(.XManE, .YManE, .ProdManE);
|
||||
@ -138,174 +137,49 @@ module fma1(
|
||||
// Alignment shifter
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
alignshift alignshift(.ZExpE, .ZManE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .ProdExpE, .Denorm,
|
||||
align align(.ZExpE, .ZManE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .ProdExpE, .Denorm,
|
||||
.AlignedAddendE, .AddendStickyE, .KillProdE);
|
||||
|
||||
|
||||
// Calculate the product's sign
|
||||
// Negate product's sign if FNMADD or FNMSUB
|
||||
|
||||
assign PSgnE = XSgnE ^ YSgnE ^ (FOpCtrlE[1]&~FOpCtrlE[2]);
|
||||
assign ZSgnEffE = ZSgnE^FOpCtrlE[0]; // Swap sign of Z for subtract
|
||||
|
||||
// calculate the signs and take the opperation into account
|
||||
sign sign(.FOpCtrlE, .XSgnE, .YSgnE, .ZSgnE, .PSgnE, .ZSgnEffE);
|
||||
|
||||
// ///////////////////////////////////////////////////////////////////////////////
|
||||
// // Addition/LZA
|
||||
// ///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
fmaadd fmaadd(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .SumE, .NegSumE, .InvZE, .NormCntE, .XZeroE, .YZeroE);
|
||||
add add(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .NegSumE, .PreSum, .NegPreSum, .InvZE, .XZeroE, .YZeroE);
|
||||
|
||||
loa loa(.AlignedAddendE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .PNormCnt, .NNormCnt);
|
||||
|
||||
// Choose the positive sum and accompanying LZA result.
|
||||
assign SumE = NegSumE ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
|
||||
assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module expadd(
|
||||
input logic FmtE, // precision
|
||||
input logic [`NE-1:0] XExpE, YExpE, // input exponents
|
||||
input logic XDenormE, YDenormE, // are the inputs denormalized
|
||||
input logic XZeroE, YZeroE, // are the inputs zero
|
||||
output logic [`NE-1:0] Denorm, // value of denormalized exponent
|
||||
output logic [`NE+1:0] ProdExpE // product's exponent B^(1023)NE+2
|
||||
);
|
||||
|
||||
logic [`NE-1:0] XExpVal, YExpVal; // Exponent value after taking into account denormals
|
||||
|
||||
// denormalized numbers have diffrent values depending on which precison it is.
|
||||
// double - 1
|
||||
// single - 1024-128+1 = 897
|
||||
assign Denorm = FmtE ? 1 : 897;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
module fma2(
|
||||
|
||||
input logic XSgnM, YSgnM, // input signs
|
||||
input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents
|
||||
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
|
||||
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic FmtM, // precision 1 = double 0 = single
|
||||
input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
|
||||
input logic AddendStickyM, // sticky bit that is calculated during alignment
|
||||
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
|
||||
input logic XZeroM, YZeroM, ZZeroM, // inputs are zero
|
||||
input logic XInfM, YInfM, ZInfM, // inputs are infinity
|
||||
input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
|
||||
input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs
|
||||
input logic [3*`NF+5:0] SumM, // the positive sum
|
||||
input logic NegSumM, // was the sum negitive
|
||||
input logic InvZM, // do you invert Z
|
||||
input logic ZSgnEffM, // the modified Z sign - depends on instruction
|
||||
input logic PSgnM, // the product's sign
|
||||
input logic [8:0] NormCntM, // the normalization shift count
|
||||
output logic [`FLEN-1:0] FMAResM, // FMA final result
|
||||
output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact}
|
||||
|
||||
|
||||
|
||||
logic [`NF-1:0] ResultFrac; // Result fraction
|
||||
logic [`NE-1:0] ResultExp; // Result exponent
|
||||
logic ResultSgn; // Result sign
|
||||
logic [`NE+1:0] SumExp; // exponent of the normalized sum
|
||||
logic [`NE+1:0] FullResultExp; // ResultExp with bits to determine sign and overflow
|
||||
logic [`NF+2:0] NormSum; // normalized sum
|
||||
logic NormSumSticky; // sticky bit calulated from the normalized sum
|
||||
logic SumZero; // is the sum zero
|
||||
logic ResultDenorm; // is the result denormalized
|
||||
logic Sticky, UfSticky; // Sticky bit
|
||||
logic Plus1, Minus1, CalcPlus1; // do you add or subtract one for rounding
|
||||
logic UfPlus1; // do you add one (for determining underflow flag)
|
||||
logic Invalid,Underflow,Overflow; // flags
|
||||
logic ZeroSgn; // the result's sign if the sum is zero
|
||||
logic ResultSgnTmp; // the result's sign assuming the result is not zero
|
||||
logic Guard, Round; // bits needed to determine rounding
|
||||
logic UfRound, UfLSBNormSum; // bits needed to determine rounding for underflow flag
|
||||
logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Normalization
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum,
|
||||
.SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Rounding
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// round to nearest even
|
||||
// round to zero
|
||||
// round to -infinity
|
||||
// round to infinity
|
||||
// round to nearest max magnitude
|
||||
|
||||
fmaround fmaround(.FmtM, .FrmM, .Sticky, .UfSticky, .NormSum, .AddendStickyM, .NormSumSticky, .ZZeroM, .InvZM, .ResultSgn, .SumExp,
|
||||
.CalcPlus1, .Plus1, .UfPlus1, .Minus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .UfRound, .UfLSBNormSum);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Sign calculation
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Determine the sign if the sum is zero
|
||||
// if cancelation then 0 unless round to -infinity
|
||||
// otherwise psign
|
||||
assign ZeroSgn = (PSgnM^ZSgnEffM)&~Underflow ? FrmM[1:0] == 2'b10 : PSgnM;
|
||||
|
||||
// is the result negitive
|
||||
// if p - z is the Sum negitive
|
||||
// if -p + z is the Sum positive
|
||||
// if -p - z then the Sum is negitive
|
||||
assign ResultSgnTmp = InvZM&(ZSgnEffM)&NegSumM | InvZM&PSgnM&~NegSumM | ((ZSgnEffM)&PSgnM);
|
||||
assign ResultSgn = SumZero ? ZeroSgn : ResultSgnTmp;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Flags
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
fmaflags fmaflags(.XSNaNM, .YSNaNM, .ZSNaNM, .XInfM, .YInfM, .ZInfM, .XZeroM, .YZeroM,
|
||||
.XNaNM, .YNaNM, .ZNaNM, .FullResultExp, .SumExp, .ZSgnEffM, .PSgnM, .Round, .Guard, .UfRound, .UfLSBNormSum, .Sticky, .UfPlus1,
|
||||
.FmtM, .Invalid, .Overflow, .Underflow, .FMAFlgM);
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Select the result
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
|
||||
assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
|
||||
assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
|
||||
assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
|
||||
{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
|
||||
((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} :
|
||||
{{32{1'b1}}, ResultSgn, 8'hff, 23'b0};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + (CalcPlus1&(AddendStickyM|FrmM[1])) : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign FMAResM = XNaNM ? XNaNResult :
|
||||
YNaNM ? YNaNResult :
|
||||
ZNaNM ? ZNaNResult :
|
||||
Invalid ? InvalidResult :
|
||||
XInfM ? FmtM ? {PSgnM, XExpM, XManM[`NF-1:0]} : {{32{1'b1}}, PSgnM, XExpM[7:0], XManM[51:29]} :
|
||||
YInfM ? FmtM ? {PSgnM, YExpM, YManM[`NF-1:0]} : {{32{1'b1}}, PSgnM, YExpM[7:0], YManM[51:29]} :
|
||||
ZInfM ? FmtM ? {ZSgnEffM, ZExpM, ZManM[`NF-1:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], ZManM[51:29]} :
|
||||
KillProdM ? KillProdResult :
|
||||
Overflow ? OverflowResult :
|
||||
Underflow & ~ResultDenorm & (ResultExp!=1) ? UnderflowResult :
|
||||
FmtM ? {ResultSgn, ResultExp, ResultFrac} :
|
||||
{{32{1'b1}}, ResultSgn, ResultExp[7:0], ResultFrac[51:29]};
|
||||
|
||||
// *** use NF where needed
|
||||
// pick denormalized value or exponent
|
||||
assign XExpVal = XDenormE ? Denorm : XExpE;
|
||||
assign YExpVal = YDenormE ? Denorm : YExpE;
|
||||
// kill the exponent if the product is zero - either X or Y is 0
|
||||
assign ProdExpE = (XExpVal + YExpVal - `NE'h3ff)&{`NE+2{~(XZeroE|YZeroE)}};
|
||||
|
||||
endmodule
|
||||
|
||||
@ -313,7 +187,6 @@ endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
module mult(
|
||||
input logic [`NF:0] XManE, YManE,
|
||||
output logic [2*`NF+1:0] ProdManE
|
||||
@ -325,7 +198,34 @@ endmodule
|
||||
|
||||
|
||||
|
||||
module alignshift(
|
||||
|
||||
|
||||
|
||||
module sign(
|
||||
input logic [2:0] FOpCtrlE, // precision
|
||||
input logic XSgnE, YSgnE, ZSgnE, // are the inputs denormalized
|
||||
output logic PSgnE, // the product's sign - takes opperation into account
|
||||
output logic ZSgnEffE // Z sign used in fma - takes opperation into account
|
||||
);
|
||||
|
||||
// Calculate the product's sign
|
||||
// Negate product's sign if FNMADD or FNMSUB
|
||||
|
||||
// flip is negation opperation
|
||||
assign PSgnE = XSgnE ^ YSgnE ^ (FOpCtrlE[1]&~FOpCtrlE[2]);
|
||||
// flip if subtraction
|
||||
assign ZSgnEffE = ZSgnE^FOpCtrlE[0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
module align(
|
||||
input logic [`NE-1:0] ZExpE, // biased exponents in B(NE.0) format
|
||||
input logic [`NF:0] ZManE, // fractions in U(0.NF) format]
|
||||
input logic ZDenormE, // is the input denormal
|
||||
@ -397,22 +297,25 @@ module alignshift(
|
||||
|
||||
endmodule
|
||||
|
||||
module fmaadd(
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
module add(
|
||||
input logic [3*`NF+5:0] AlignedAddendE, // Z aligned for addition in U(NF+5.2NF+1)
|
||||
input logic [2*`NF+1:0] ProdManE, // the product's mantissa
|
||||
input logic PSgnE, ZSgnEffE,// the product and modified Z signs
|
||||
input logic KillProdE, // should the product be set to 0
|
||||
input logic XZeroE, YZeroE, // is the input zero
|
||||
output logic [3*`NF+5:0] SumE, // the positive sum
|
||||
output logic [3*`NF+6:0] AlignedAddendInv, // aligned addend possibly inverted
|
||||
output logic [2*`NF+1:0] ProdManKilled, // the product's mantissa possibly killed
|
||||
output logic [3*`NF+6:0] NegProdManKilled, // a negated ProdManKilled
|
||||
output logic NegSumE, // was the sum negitive
|
||||
output logic InvZE, // do you invert Z
|
||||
output logic [8:0] NormCntE // normalization shift count
|
||||
output logic [3*`NF+6:0] PreSum, NegPreSum// possibly negitive sum
|
||||
);
|
||||
logic [3*`NF+6:0] PreSum, NegPreSum; // possibly negitive sum
|
||||
logic [2*`NF+1:0] ProdMan2; // product being added
|
||||
logic [3*`NF+6:0] AlignedAddend2; // possibly inverted aligned Z
|
||||
logic [3*`NF+6:0] NegProdMan2; // a negated ProdMan2
|
||||
logic [8:0] PNormCnt, NNormCnt; // results from the LZA
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Addition
|
||||
@ -424,36 +327,42 @@ module fmaadd(
|
||||
assign InvZE = ZSgnEffE ^ PSgnE;
|
||||
|
||||
// Choose an inverted or non-inverted addend - the one has to be added now for the LZA
|
||||
assign AlignedAddend2 = InvZE ? -{1'b0, AlignedAddendE} : {1'b0, AlignedAddendE};
|
||||
assign AlignedAddendInv = InvZE ? -{1'b0, AlignedAddendE} : {1'b0, AlignedAddendE};
|
||||
// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
|
||||
assign ProdMan2 = ProdManE&{2*`NF+2{~KillProdE}};
|
||||
assign ProdManKilled = ProdManE&{2*`NF+2{~KillProdE}};
|
||||
// Negate ProdMan for LZA and the negitive sum calculation
|
||||
assign NegProdMan2 = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, -ProdMan2, 2'b0};
|
||||
assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, -ProdManKilled, 2'b0};
|
||||
|
||||
// LZAs one for the positive result and one for the negitive
|
||||
// - the +1 from inverting causes problems for normalization
|
||||
poslza poslza(AlignedAddend2, ProdMan2, PNormCnt);
|
||||
neglza neglza({1'b0,AlignedAddendE}, NegProdMan2, NNormCnt);
|
||||
|
||||
|
||||
// Do the addition
|
||||
// - calculate a positive and negitive sum in parallel
|
||||
assign PreSum = AlignedAddend2 + {ProdMan2, 2'b0};
|
||||
assign NegPreSum = AlignedAddendE + NegProdMan2;
|
||||
assign PreSum = AlignedAddendInv + {ProdManKilled, 2'b0};
|
||||
assign NegPreSum = AlignedAddendE + NegProdManKilled;
|
||||
|
||||
// Is the sum negitive
|
||||
assign NegSumE = PreSum[3*`NF+6];
|
||||
// Choose the positive sum and accompanying LZA result.
|
||||
assign SumE = NegSumE ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
|
||||
assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module loa(
|
||||
input logic [3*`NF+5:0] AlignedAddendE, // Z aligned for addition in U(NF+5.2NF+1)
|
||||
input logic [3*`NF+6:0] AlignedAddendInv, // aligned addend possibly inverted
|
||||
input logic [2*`NF+1:0] ProdManKilled, // the product's mantissa possibly killed
|
||||
input logic [3*`NF+6:0] NegProdManKilled, // a negated ProdManKilled
|
||||
output logic [8:0] PNormCnt, NNormCnt // positive and negitive LOA result
|
||||
);
|
||||
|
||||
// LZAs one for the positive result and one for the negitive
|
||||
// - the +1 from inverting causes problems for normalization
|
||||
posloa posloa(AlignedAddendInv, ProdManKilled, PNormCnt);
|
||||
negloa negloa({1'b0,AlignedAddendE}, NegProdManKilled, NNormCnt);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
module poslza(
|
||||
module posloa(
|
||||
input logic [3*`NF+6:0] A, // addend
|
||||
input logic [2*`NF+1:0] P, // product
|
||||
output logic [8:0] PCnt // normalization shift count for the positive result
|
||||
@ -484,7 +393,7 @@ module poslza(
|
||||
|
||||
endmodule
|
||||
|
||||
module neglza(
|
||||
module negloa(
|
||||
input logic [3*`NF+6:0] A, // addend
|
||||
input logic [3*`NF+6:0] P, // product
|
||||
output logic [8:0] NCnt // normalization shift count for the negitive result
|
||||
@ -512,6 +421,197 @@ endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
module fma2(
|
||||
|
||||
input logic XSgnM, YSgnM, // input signs
|
||||
input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents
|
||||
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
|
||||
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic FmtM, // precision 1 = double 0 = single
|
||||
input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
|
||||
input logic AddendStickyM, // sticky bit that is calculated during alignment
|
||||
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
|
||||
input logic XZeroM, YZeroM, ZZeroM, // inputs are zero
|
||||
input logic XInfM, YInfM, ZInfM, // inputs are infinity
|
||||
input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
|
||||
input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs
|
||||
input logic [3*`NF+5:0] SumM, // the positive sum
|
||||
input logic NegSumM, // was the sum negitive
|
||||
input logic InvZM, // do you invert Z
|
||||
input logic ZSgnEffM, // the modified Z sign - depends on instruction
|
||||
input logic PSgnM, // the product's sign
|
||||
input logic [8:0] NormCntM, // the normalization shift count
|
||||
output logic [`FLEN-1:0] FMAResM, // FMA final result
|
||||
output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact}
|
||||
|
||||
|
||||
|
||||
logic [`NF-1:0] ResultFrac; // Result fraction
|
||||
logic [`NE-1:0] ResultExp; // Result exponent
|
||||
logic ResultSgn; // Result sign
|
||||
logic [`NE+1:0] SumExp; // exponent of the normalized sum
|
||||
logic [`NE+1:0] FullResultExp; // ResultExp with bits to determine sign and overflow
|
||||
logic [`NF+2:0] NormSum; // normalized sum
|
||||
logic NormSumSticky; // sticky bit calulated from the normalized sum
|
||||
logic SumZero; // is the sum zero
|
||||
logic ResultDenorm; // is the result denormalized
|
||||
logic Sticky, UfSticky; // Sticky bit
|
||||
logic Plus1, Minus1, CalcPlus1; // do you add or subtract one for rounding
|
||||
logic UfPlus1; // do you add one (for determining underflow flag)
|
||||
logic Invalid,Underflow,Overflow; // flags
|
||||
logic ZeroSgn; // the result's sign if the sum is zero
|
||||
logic ResultSgnTmp; // the result's sign assuming the result is not zero
|
||||
logic Guard, Round; // bits needed to determine rounding
|
||||
logic UfRound, UfLSBNormSum; // bits needed to determine rounding for underflow flag
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Normalization
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum,
|
||||
.SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Rounding
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// round to nearest even
|
||||
// round to zero
|
||||
// round to -infinity
|
||||
// round to infinity
|
||||
// round to nearest max magnitude
|
||||
|
||||
fmaround fmaround(.FmtM, .FrmM, .Sticky, .UfSticky, .NormSum, .AddendStickyM, .NormSumSticky, .ZZeroM, .InvZM, .ResultSgn, .SumExp,
|
||||
.CalcPlus1, .Plus1, .UfPlus1, .Minus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .UfRound, .UfLSBNormSum);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Sign calculation
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
resultsign resultsign(.FrmM, .PSgnM, .ZSgnEffM, .Underflow, .InvZM, .NegSumM, .SumZero, .ResultSgn);
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Flags
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
fmaflags fmaflags(.XSNaNM, .YSNaNM, .ZSNaNM, .XInfM, .YInfM, .ZInfM, .XZeroM, .YZeroM,
|
||||
.XNaNM, .YNaNM, .ZNaNM, .FullResultExp, .SumExp, .ZSgnEffM, .PSgnM, .Round, .Guard, .UfRound, .UfLSBNormSum, .Sticky, .UfPlus1,
|
||||
.FmtM, .Invalid, .Overflow, .Underflow, .FMAFlgM);
|
||||
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Select the result
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
resultselect resultselect(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
|
||||
.FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM,
|
||||
.ZSgnEffM, .PSgnM, .ResultSgn, .Minus1, .Plus1, .CalcPlus1, .Invalid, .Overflow, .Underflow,
|
||||
.ResultDenorm, .ResultExp, .ResultFrac, .FMAResM);
|
||||
|
||||
// *** use NF where needed
|
||||
|
||||
endmodule
|
||||
|
||||
module resultsign(
|
||||
input logic [2:0] FrmM,
|
||||
input logic PSgnM, ZSgnEffM,
|
||||
input logic Underflow,
|
||||
input logic InvZM,
|
||||
input logic NegSumM,
|
||||
input logic SumZero,
|
||||
output logic ResultSgn
|
||||
);
|
||||
|
||||
logic ZeroSgn;
|
||||
logic ResultSgnTmp;
|
||||
|
||||
// Determine the sign if the sum is zero
|
||||
// if cancelation then 0 unless round to -infinity
|
||||
// otherwise psign
|
||||
assign ZeroSgn = (PSgnM^ZSgnEffM)&~Underflow ? FrmM[1:0] == 2'b10 : PSgnM;
|
||||
|
||||
// is the result negitive
|
||||
// if p - z is the Sum negitive
|
||||
// if -p + z is the Sum positive
|
||||
// if -p - z then the Sum is negitive
|
||||
assign ResultSgnTmp = InvZM&(ZSgnEffM)&NegSumM | InvZM&PSgnM&~NegSumM | ((ZSgnEffM)&PSgnM);
|
||||
assign ResultSgn = SumZero ? ZeroSgn : ResultSgnTmp;
|
||||
|
||||
endmodule
|
||||
|
||||
module resultselect(
|
||||
input logic XSgnM, YSgnM, // input signs
|
||||
input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents
|
||||
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
|
||||
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic FmtM, // precision 1 = double 0 = single
|
||||
input logic AddendStickyM, // sticky bit that is calculated during alignment
|
||||
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
|
||||
input logic XInfM, YInfM, ZInfM, // inputs are infinity
|
||||
input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
|
||||
input logic ZSgnEffM, // the modified Z sign - depends on instruction
|
||||
input logic PSgnM, // the product's sign
|
||||
input logic ResultSgn, // the result's sign
|
||||
input logic Minus1, Plus1, CalcPlus1, // rounding bits
|
||||
input logic Invalid, Overflow, Underflow, // flags
|
||||
input logic ResultDenorm, // is the result denormalized
|
||||
input logic [`NE-1:0] ResultExp, // Result exponent
|
||||
input logic [`NF-1:0] ResultFrac, // Result fraction
|
||||
output logic [`FLEN-1:0] FMAResM // FMA final result
|
||||
);
|
||||
logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
|
||||
|
||||
assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
|
||||
assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
|
||||
assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
|
||||
assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
|
||||
{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
|
||||
((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} :
|
||||
{{32{1'b1}}, ResultSgn, 8'hff, 23'b0};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + (CalcPlus1&(AddendStickyM|FrmM[1])) : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign FMAResM = XNaNM ? XNaNResult :
|
||||
YNaNM ? YNaNResult :
|
||||
ZNaNM ? ZNaNResult :
|
||||
Invalid ? InvalidResult :
|
||||
XInfM ? FmtM ? {PSgnM, XExpM, XManM[`NF-1:0]} : {{32{1'b1}}, PSgnM, XExpM[7:0], XManM[51:29]} :
|
||||
YInfM ? FmtM ? {PSgnM, YExpM, YManM[`NF-1:0]} : {{32{1'b1}}, PSgnM, YExpM[7:0], YManM[51:29]} :
|
||||
ZInfM ? FmtM ? {ZSgnEffM, ZExpM, ZManM[`NF-1:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], ZManM[51:29]} :
|
||||
KillProdM ? KillProdResult :
|
||||
Overflow ? OverflowResult :
|
||||
Underflow & ~ResultDenorm & (ResultExp!=1) ? UnderflowResult :
|
||||
FmtM ? {ResultSgn, ResultExp, ResultFrac} :
|
||||
{{32{1'b1}}, ResultSgn, ResultExp[7:0], ResultFrac[51:29]};
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module normalize(
|
||||
input logic [3*`NF+5:0] SumM, // the positive sum
|
||||
input logic [`NE-1:0] ZExpM, // exponent of Z
|
||||
|
@ -1,92 +1,86 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// File name : fpdiv
|
||||
// Title : Floating-Point Divider/Square-Root
|
||||
// project : FPU
|
||||
// Library : fpdiv
|
||||
// Author(s) : James E. Stine, Jr.
|
||||
// Purpose : definition of main unit to floating-point div/sqrt
|
||||
// notes :
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Copyright Oklahoma State University
|
||||
// Purpose: Floating point divider/square root top unit (Goldschmidt)
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Basic Operations
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// Step 1: Load operands, set flags, and convert SP to DP
|
||||
// Step 2: Check for special inputs ( +/- Infinity, NaN)
|
||||
// Step 3: Exponent Logic
|
||||
// Step 4: Divide/Sqrt using Goldschmidt
|
||||
// Step 5: Normalize the result.//
|
||||
// Shift left until normalized. Normalized when the value to the
|
||||
// left of the binrary point is 1.
|
||||
// Step 6: Round the result.//
|
||||
// Step 7: Put quotient/remainder onto output.
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// `timescale 1ps/1ps
|
||||
module fpdiv (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
input logic [63:0] op1, // 1st input operand (A)
|
||||
input logic [63:0] op2, // 2nd input operand (B)
|
||||
input logic [1:0] rm, // Rounding mode - specify values
|
||||
input logic op_type, // Function opcode
|
||||
input logic P, // Result Precision (0 for double, 1 for single)
|
||||
input logic OvEn, // Overflow trap enabled
|
||||
input logic UnEn, // Underflow trap enabled
|
||||
output logic done,
|
||||
output logic FDivBusyE,
|
||||
output logic [63:0] AS_Result, // Result of operation
|
||||
output logic [4:0] Flags); // IEEE exception flags
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
input logic [63:0] op1,
|
||||
input logic [63:0] op2,
|
||||
input logic [1:0] rm,
|
||||
input logic op_type,
|
||||
input logic P,
|
||||
input logic OvEn,
|
||||
input logic UnEn,
|
||||
input logic XNaNQ,
|
||||
input logic YNaNQ,
|
||||
input logic XZeroQ,
|
||||
input logic YZeroQ,
|
||||
input logic XInfQ,
|
||||
input logic YInfQ,
|
||||
|
||||
|
||||
logic [63:0] Float1;
|
||||
logic [63:0] Float2;
|
||||
output logic done,
|
||||
output logic FDivBusyE,
|
||||
output logic [63:0] AS_Result,
|
||||
output logic [4:0] Flags);
|
||||
|
||||
logic [12:0] exp1, exp2, expF;
|
||||
logic [12:0] exp_diff, bias;
|
||||
logic [13:0] exp_sqrt;
|
||||
logic [12:0] exp_s;
|
||||
logic [12:0] exp_c;
|
||||
logic [63:0] Float1;
|
||||
logic [63:0] Float2;
|
||||
|
||||
logic [10:0] exponent;
|
||||
logic [63:0] Result;
|
||||
logic [52:0] mantissaA;
|
||||
logic [52:0] mantissaB;
|
||||
logic [12:0] exp1, exp2, expF;
|
||||
logic [12:0] exp_diff, bias;
|
||||
logic [13:0] exp_sqrt;
|
||||
logic [63:0] Result;
|
||||
logic [52:0] mantissaA;
|
||||
logic [52:0] mantissaB;
|
||||
|
||||
logic [2:0] sel_inv;
|
||||
logic Invalid;
|
||||
logic [4:0] FlagsIn;
|
||||
logic [2:0] sel_inv;
|
||||
logic Invalid;
|
||||
logic [4:0] FlagsIn;
|
||||
logic signResult;
|
||||
logic convert;
|
||||
logic sub;
|
||||
logic sub;
|
||||
|
||||
logic [63:0] q1, qm1, qp1, q0, qm0, qp0;
|
||||
logic [63:0] rega_out, regb_out, regc_out, regd_out;
|
||||
logic [127:0] regr_out;
|
||||
logic [2:0] sel_muxa, sel_muxb;
|
||||
logic [63:0] q1, qm1, qp1, q0, qm0, qp0;
|
||||
logic [63:0] rega_out, regb_out, regc_out, regd_out;
|
||||
logic [127:0] regr_out;
|
||||
logic [2:0] sel_muxa, sel_muxb;
|
||||
logic sel_muxr;
|
||||
logic load_rega, load_regb, load_regc, load_regd, load_regr;
|
||||
|
||||
logic load_regs;
|
||||
logic exp_cout1, exp_cout2;
|
||||
logic exp_odd, open;
|
||||
|
||||
// div/sqrt
|
||||
// fdiv = 0
|
||||
// fsqrt = 1
|
||||
logic load_regs;
|
||||
logic exp_cout1, exp_cout2;
|
||||
logic exp_odd, open;
|
||||
|
||||
// op_type : fdiv=0, fsqrt=1
|
||||
assign Float1 = op1;
|
||||
assign Float2 = op_type ? op1 : op2;
|
||||
|
||||
// Test for exceptions and return the "Invalid Operation" and
|
||||
// "Denormalized" Input Flags. The "sel_inv" is used in
|
||||
// the third pipeline stage to select the result. Also, op1_Norm
|
||||
// and op2_Norm are one if op1 and op2 are not zero or denormalized.
|
||||
// sub is one if the effective operation is subtaction.
|
||||
exception_div exc1 (.A(Float1), .B(Float2), .op_type,
|
||||
// output:
|
||||
.Ztype(sel_inv), .Invalid);
|
||||
|
||||
|
||||
// Exception detection
|
||||
exception_div exc1 (.A(Float1), .B(Float2), .op_type, .Ztype(sel_inv), .Invalid);
|
||||
|
||||
// Determine Sign/Mantissa
|
||||
assign signResult = (Float1[63]^Float2[63]);
|
||||
assign mantissaA = {1'b1, Float1[51:0]};
|
||||
@ -103,29 +97,30 @@ module fpdiv (
|
||||
assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + exp_odd;
|
||||
// Choose correct exponent
|
||||
assign expF = op_type ? exp_sqrt[13:1] : exp_diff;
|
||||
|
||||
|
||||
// Main Goldschmidt/Division Routine
|
||||
divconv goldy (.q1, .qm1, .qp1, .q0, .qm0, .qp0, .rega_out, .regb_out, .regc_out, .regd_out,
|
||||
.regr_out, .d(mantissaB), .n(mantissaA), .sel_muxa, .sel_muxb, .sel_muxr,
|
||||
.reset, .clk, .load_rega, .load_regb, .load_regc, .load_regd,
|
||||
.load_regr, .load_regs, .P, .op_type, .exp_odd);
|
||||
|
||||
|
||||
// FSM : control divider
|
||||
fsm control (.clk, .reset, .start, .op_type,
|
||||
// outputs:
|
||||
.done, .load_rega, .load_regb, .load_regc, .load_regd,
|
||||
.load_regr, .load_regs, .sel_muxa, .sel_muxb, .sel_muxr,
|
||||
.divBusy(FDivBusyE));
|
||||
.done, .load_rega, .load_regb, .load_regc, .load_regd,
|
||||
.load_regr, .load_regs, .sel_muxa, .sel_muxb, .sel_muxr,
|
||||
.divBusy(FDivBusyE));
|
||||
|
||||
// Round the mantissa to a 52-bit value, with the leading one
|
||||
// removed. The rounding units also handles special cases and
|
||||
// set the exception flags.
|
||||
rounder_div round1 (.rm, .P, .OvEn, .UnEn, .exp_diff(expF),
|
||||
.sel_inv, .Invalid, .SignR(signResult),
|
||||
.q1, .qm1, .qp1, .q0, .qm0, .qp0, .regr_out,
|
||||
// outputs:
|
||||
.Result, .Flags(FlagsIn));
|
||||
|
||||
.sel_inv, .Invalid, .SignR(signResult),
|
||||
.Float1(op1), .Float2(op2),
|
||||
.XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ,
|
||||
.XInfQ, .YInfQ, .op_type,
|
||||
.q1, .qm1, .qp1, .q0, .qm0, .qp0, .regr_out,
|
||||
.Result, .Flags(FlagsIn));
|
||||
|
||||
// Store the final result and the exception flags in registers.
|
||||
flopenr #(64) rega (clk, reset, done, Result, AS_Result);
|
||||
flopenr #(5) regc (clk, reset, done, FlagsIn, Flags);
|
||||
|
@ -1,6 +1,6 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: Katherine Parry, Bret Mathis
|
||||
// Written: Katherine Parry, James Stine, Brett Mathis
|
||||
// Modified: 6/23/2021
|
||||
//
|
||||
// Purpose: FPU
|
||||
@ -25,24 +25,24 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fpu (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic [2:0] FRM_REGW, // Rounding mode from CSR
|
||||
input logic [31:0] InstrD, // instruction from IFU
|
||||
input logic [`XLEN-1:0] ReadDataW,// Read data from memory
|
||||
input logic [`XLEN-1:0] SrcAE, // Integer input being processed (from IEU)
|
||||
input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg (from IEU)
|
||||
input logic StallE, StallM, StallW, // stall signals from HZU
|
||||
input logic FlushE, FlushM, FlushW, // flush signals from HZU
|
||||
input logic [4:0] RdE, RdM, RdW, // which FP register to write to (from IEU)
|
||||
output logic FRegWriteM, // FP register write enable
|
||||
output logic FStallD, // Stall the decode stage
|
||||
output logic FWriteIntE, FWriteIntM, FWriteIntW, // integer register write enable
|
||||
output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory
|
||||
output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
|
||||
output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
||||
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
||||
output logic [4:0] SetFflagsM // FMA flags (to privileged unit)
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic [2:0] FRM_REGW, // Rounding mode from CSR
|
||||
input logic [31:0] InstrD, // instruction from IFU
|
||||
input logic [`XLEN-1:0] ReadDataW,// Read data from memory
|
||||
input logic [`XLEN-1:0] SrcAE, // Integer input being processed (from IEU)
|
||||
input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg (from IEU)
|
||||
input logic StallE, StallM, StallW, // stall signals from HZU
|
||||
input logic FlushE, FlushM, FlushW, // flush signals from HZU
|
||||
input logic [4:0] RdE, RdM, RdW, // which FP register to write to (from IEU)
|
||||
output logic FRegWriteM, // FP register write enable
|
||||
output logic FStallD, // Stall the decode stage
|
||||
output logic FWriteIntE, FWriteIntM, FWriteIntW, // integer register write enable
|
||||
output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory
|
||||
output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
|
||||
output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
||||
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
||||
output logic [4:0] SetFflagsM // FMA flags (to privileged unit)
|
||||
);
|
||||
|
||||
//*** make everything FLEN at some point
|
||||
@ -59,338 +59,260 @@ module fpu (
|
||||
|
||||
generate if (`F_SUPPORTED | `D_SUPPORTED) begin : fpu
|
||||
|
||||
// control signals
|
||||
logic FRegWriteD, FRegWriteE, FRegWriteW; // FP register write enable
|
||||
logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode
|
||||
logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
|
||||
logic FDivStartD, FDivStartE; // Start division or squareroot
|
||||
logic FWriteIntD; // Write to integer register
|
||||
logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
|
||||
logic [1:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select the result written to FP register
|
||||
logic [2:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
|
||||
logic [2:0] FResSelD, FResSelE, FResSelM; // Select one of the results that finish in the memory stage
|
||||
logic [1:0] FIntResSelD, FIntResSelE, FIntResSelM; // Select the result written to the integer resister
|
||||
logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
|
||||
// control signals
|
||||
logic FRegWriteD, FRegWriteE, FRegWriteW; // FP register write enable
|
||||
logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode
|
||||
logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
|
||||
logic FDivStartD, FDivStartE; // Start division or squareroot
|
||||
logic FWriteIntD; // Write to integer register
|
||||
logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
|
||||
logic [1:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select the result written to FP register
|
||||
logic [2:0] FOpCtrlD, FOpCtrlE, FOpCtrlM; // Select which opperation to do in each component
|
||||
logic [2:0] FResSelD, FResSelE, FResSelM; // Select one of the results that finish in the memory stage
|
||||
logic [1:0] FIntResSelD, FIntResSelE, FIntResSelM; // Select the result written to the integer resister
|
||||
logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
|
||||
|
||||
// regfile signals
|
||||
logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
|
||||
logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
|
||||
logic [63:0] FSrcXE, FSrcXM; // Input 1 to the various units (after forwarding)
|
||||
logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
|
||||
logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
|
||||
|
||||
// unpacking signals
|
||||
logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
|
||||
logic XSgnM, YSgnM; // input's sign - memory stage
|
||||
logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
|
||||
logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage
|
||||
logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
|
||||
logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
|
||||
logic [10:0] BiasE; // bias based on precision (single=7f double=3ff - max expoent/2)
|
||||
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
|
||||
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
|
||||
logic XNaNQ, YNaNQ; // is the input a NaN - divide
|
||||
logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
|
||||
logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
|
||||
logic XDenormE, YDenormE, ZDenormE; // is the input denormalized
|
||||
logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
|
||||
logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage
|
||||
logic XZeroQ, YZeroQ; // is the input zero - divide
|
||||
logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
|
||||
logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
|
||||
logic XInfQ, YInfQ; // is the input infinity - divide
|
||||
logic XExpMaxE; // is the exponent all ones (max value)
|
||||
logic XNormE; // is normal
|
||||
|
||||
// result and flag signals
|
||||
logic [63:0] FDivResM, FDivResW; // divide/squareroot result
|
||||
logic [4:0] FDivFlgM, FDivFlgW; // divide/squareroot flags
|
||||
logic [63:0] FMAResM, FMAResW; // FMA/multiply result
|
||||
logic [4:0] FMAFlgM, FMAFlgW; // FMA/multiply result
|
||||
logic [63:0] ReadResW; // read result (load instruction)
|
||||
logic [63:0] CvtFpResE, CvtFpResM, CvtFpResW; // add/FP -> FP convert result
|
||||
logic [4:0] CvtFpFlgE, CvtFpFlgM, CvtFpFlgW; // add/FP -> FP convert flags
|
||||
logic [63:0] CvtResE, CvtResM; // FP <-> int convert result
|
||||
logic [4:0] CvtFlgE, CvtFlgM; // FP <-> int convert flags //*** trim this
|
||||
logic [63:0] ClassResE, ClassResM; // classify result
|
||||
logic [63:0] CmpResE, CmpResM; // compare result
|
||||
logic CmpNVE, CmpNVM; // compare invalid flag (Not Valid)
|
||||
logic [63:0] SgnResE, SgnResM; // sign injection result
|
||||
logic SgnNVE, SgnNVM; // sign injection invalid flag (Not Valid)
|
||||
logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
|
||||
logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
|
||||
logic [`XLEN-1:0] FIntResE;
|
||||
logic [63:0] FPUResultW; // final FP result being written to the FP register
|
||||
|
||||
// other signals
|
||||
logic FDivSqrtDoneE; // is divide done
|
||||
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
|
||||
logic FDivClk; // clock for divide/squareroot unit
|
||||
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
|
||||
|
||||
// DECODE STAGE
|
||||
// calculate FP control signals
|
||||
fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .FRM_REGW,
|
||||
.IllegalFPUInstrD, .FRegWriteD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD,
|
||||
.FIntResSelD, .FmtD, .FrmD, .FWriteIntD);
|
||||
|
||||
// regfile signals
|
||||
logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
|
||||
logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
|
||||
logic [63:0] FSrcXE, FSrcXM; // Input 1 to the various units (after forwarding)
|
||||
logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
|
||||
logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
|
||||
|
||||
// unpacking signals
|
||||
logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
|
||||
logic XSgnM, YSgnM; // input's sign - memory stage
|
||||
logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
|
||||
logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage
|
||||
logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
|
||||
logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
|
||||
logic [10:0] BiasE; // bias based on precision (single=7f double=3ff - max expoent/2)
|
||||
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
|
||||
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
|
||||
logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage
|
||||
logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage
|
||||
logic XDenormE, YDenormE, ZDenormE; // is the input denormalized
|
||||
logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage
|
||||
logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage
|
||||
logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage
|
||||
logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage
|
||||
logic XExpMaxE; // is the exponent all ones (max value)
|
||||
logic XNormE; // is normal
|
||||
|
||||
|
||||
// result and flag signals
|
||||
logic [63:0] FDivResM, FDivResW; // divide/squareroot result
|
||||
logic [4:0] FDivFlgM, FDivFlgW; // divide/squareroot flags
|
||||
// FP register file
|
||||
// - can read 3 registers and write 1 register every cycle
|
||||
fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
|
||||
.a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), .a4(RdW),
|
||||
.wd4(FPUResultW),
|
||||
.rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));
|
||||
|
||||
// D/E pipeline registers
|
||||
flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
|
||||
flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
|
||||
flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
|
||||
flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
|
||||
{Adr1E, Adr2E, Adr3E});
|
||||
flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD},
|
||||
{FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE});
|
||||
|
||||
// EXECUTION STAGE
|
||||
// Hazard unit for FPU
|
||||
// - determines if any forwarding or stalls are needed
|
||||
fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResultSelM,
|
||||
.FStallD, .FForwardXE, .FForwardYE, .FForwardZE);
|
||||
|
||||
// forwarding muxs
|
||||
mux3 #(64) fxemux(FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
|
||||
mux3 #(64) fyemux(FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
|
||||
mux3 #(64) fzemux(FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
|
||||
mux3 #(64) fyaddmux(FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0},
|
||||
{2'b0, {10{1'b1}}, 52'b0},
|
||||
{FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==3'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==3'b01)},
|
||||
FSrcYE); // Force Z to be 0 for multiply instructions
|
||||
// Force Z to be 0 for multiply instructions
|
||||
mux3 #(64) fzmulmux(FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
|
||||
|
||||
// unpacking unit
|
||||
// - splits FP inputs into their various parts
|
||||
// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
|
||||
unpacking unpacking(.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE,
|
||||
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
|
||||
.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
|
||||
|
||||
// FMA
|
||||
// - two stage FMA
|
||||
// - execute stage - multiplication and addend shifting
|
||||
// - memory stage - addition and rounding
|
||||
// - handles FMA and multiply instructions
|
||||
fma fma (.clk, .reset, .FlushM, .StallM,
|
||||
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
|
||||
.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
|
||||
.XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM,
|
||||
.XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
|
||||
.FOpCtrlE,
|
||||
.FmtE, .FmtM, .FrmM,
|
||||
.FMAFlgM, .FMAResM);
|
||||
|
||||
// clock gater
|
||||
// - creates a clock that only runs durring divide/sqrt instructions
|
||||
// - using the seperate clock gives the divide/sqrt unit some to get set up
|
||||
// *** the module says not to use in synthisis
|
||||
clockgater fpdivclkg(.E(FDivStartE),
|
||||
.SE(1'b0),
|
||||
.CLK(clk),
|
||||
.ECLK(FDivClk));
|
||||
|
||||
// capture the inputs for divide/sqrt
|
||||
// - if not captured any forwarded inputs will change durring computation
|
||||
// - this problem is caused by stalling the execute stage
|
||||
// - the other units don't have this problem, only div/sqrt stalls the execute stage
|
||||
floprc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
|
||||
.clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(FDivBusyE));
|
||||
floprc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
|
||||
.clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(FDivBusyE));
|
||||
floprc #(6) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE}),
|
||||
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ}),
|
||||
.clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(FDivBusyE));
|
||||
|
||||
// fpdivsqrt using Goldschmidt's iteration
|
||||
fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
|
||||
.reset, .clk(FDivClk), .start(FDivStartE), .P(~FmtE), .OvEn(1'b1), .UnEn(1'b1),
|
||||
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ,
|
||||
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
|
||||
|
||||
// convert from signle to double and vice versa
|
||||
cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
|
||||
|
||||
// compare unit
|
||||
// - computation is done in one stage
|
||||
// - writes to FP file durring min/max instructions
|
||||
// - other comparisons write a 1 or 0 to the integer register
|
||||
fcmp fcmp (.op1({XSgnE,XExpE,XManE[`NF-1:0]}), .op2({YSgnE,YExpE,YManE[`NF-1:0]}),
|
||||
.FSrcXE, .FSrcYE, .FOpCtrlE,
|
||||
.FmtE, .XNaNE, .YNaNE, .XZeroE, .YZeroE,
|
||||
.Invalid(CmpNVE), .CmpResE);
|
||||
|
||||
// sign injection unit
|
||||
// - computation is done in one stage
|
||||
fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE,
|
||||
.SgnNVE, .SgnResE);
|
||||
|
||||
// classify
|
||||
// - computation is done in one stage
|
||||
// - most of the work is done in the unpacking unit
|
||||
// - result is written to the integer register
|
||||
fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE,
|
||||
.XSNaNE, .ClassResE);
|
||||
|
||||
fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE,
|
||||
.CvtResE, .CvtFlgE);
|
||||
|
||||
// data to be stored in memory - to IEU
|
||||
// - FP uses NaN-blocking format
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
assign FWriteDataE = FSrcYE[`XLEN-1:0];
|
||||
|
||||
// Align SrcA to MSB when single precicion
|
||||
mux2 #(64) SrcAMux({{32{1'b1}}, SrcAE[31:0]}, {{64-`XLEN{1'b1}}, SrcAE}, FmtE, AlignedSrcAE);
|
||||
|
||||
// select a result that may be written to the FP register
|
||||
mux5 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE);
|
||||
mux5 #(5) FFlgMux(5'b0, {4'b0, SgnNVE}, {4'b0, CmpNVE}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE);
|
||||
|
||||
// select the result that may be written to the integer register - to IEU
|
||||
mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0],
|
||||
CvtResE[`XLEN-1:0], FIntResSelE, FIntResE);
|
||||
|
||||
// E/M pipe registers
|
||||
|
||||
// flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM);
|
||||
flopenrc #(65) EMFpReg2(clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM});
|
||||
flopenrc #(65) EMFpReg3(clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM});
|
||||
flopenrc #(64) EMFpReg4(clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
|
||||
flopenrc #(12) EMFpReg5(clk, reset, FlushM, ~StallM,
|
||||
{XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
|
||||
{XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
|
||||
flopenrc #(64) EMRegCmpRes(clk, reset, FlushM, ~StallM, FResE, FResM);
|
||||
flopenrc #(5) EMRegCmpFlg(clk, reset, FlushM, ~StallM, FFlgE, FFlgM);
|
||||
flopenrc #(`XLEN) EMRegSgnRes(clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
|
||||
flopenrc #(11) EMCtrlReg(clk, reset, FlushM, ~StallM,
|
||||
{FRegWriteE, FResultSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE},
|
||||
{FRegWriteM, FResultSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM});
|
||||
|
||||
// BEGIN MEMORY STAGE
|
||||
// FPU flag selection - to privileged
|
||||
mux4 #(5) FPUFlgMux(5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM);
|
||||
|
||||
logic [63:0] FMAResM, FMAResW; // FMA/multiply result
|
||||
logic [4:0] FMAFlgM, FMAFlgW; // FMA/multiply result
|
||||
|
||||
logic [63:0] ReadResW; // read result (load instruction)
|
||||
// M/W pipe registers
|
||||
flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
|
||||
flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW);
|
||||
flopenrc #(64) MWRegAdd(clk, reset, FlushW, ~StallW, CvtFpResM, CvtFpResW);
|
||||
flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
|
||||
flopenrc #(5) MWCtrlReg(clk, reset, FlushW, ~StallW,
|
||||
{FRegWriteM, FResultSelM, FmtM, FWriteIntM},
|
||||
{FRegWriteW, FResultSelW, FmtW, FWriteIntW});
|
||||
|
||||
// BEGIN WRITEBACK STAGE
|
||||
|
||||
// put ReadData into NaN-blocking format
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
// - for load instruction
|
||||
mux2 #(64) ReadResMux({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
|
||||
|
||||
// select the result to be written to the FP register
|
||||
mux4 #(64) FPUResultMux(ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW);
|
||||
|
||||
logic [63:0] CvtFpResE, CvtFpResM, CvtFpResW; // add/FP -> FP convert result
|
||||
logic [4:0] CvtFpFlgE, CvtFpFlgM, CvtFpFlgW; // add/FP -> FP convert flags
|
||||
|
||||
logic [63:0] CvtResE, CvtResM; // FP <-> int convert result
|
||||
logic [4:0] CvtFlgE, CvtFlgM; // FP <-> int convert flags //*** trim this
|
||||
|
||||
logic [63:0] ClassResE, ClassResM; // classify result
|
||||
|
||||
logic [63:0] CmpResE, CmpResM; // compare result
|
||||
logic CmpNVE, CmpNVM; // compare invalid flag (Not Valid)
|
||||
|
||||
logic [63:0] SgnResE, SgnResM; // sign injection result
|
||||
logic SgnNVE, SgnNVM; // sign injection invalid flag (Not Valid)
|
||||
|
||||
logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
|
||||
logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
|
||||
|
||||
logic [`XLEN-1:0] FIntResE;
|
||||
|
||||
logic [63:0] FPUResultW; // final FP result being written to the FP register
|
||||
|
||||
// other signals
|
||||
logic FDivSqrtDoneE; // is divide done
|
||||
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
|
||||
logic FDivClk; // clock for divide/squareroot unit
|
||||
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
//DECODE STAGE
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
// calculate FP control signals
|
||||
fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .FRM_REGW,
|
||||
// outputs:
|
||||
.IllegalFPUInstrD, .FRegWriteD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD,
|
||||
.FIntResSelD, .FmtD, .FrmD, .FWriteIntD);
|
||||
|
||||
// FP register file
|
||||
// - can read 3 registers and write 1 register every cycle
|
||||
fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
|
||||
.a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), .a4(RdW),
|
||||
.wd4(FPUResultW),
|
||||
// outputs:
|
||||
.rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
// D/E pipeline registers
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
|
||||
flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
|
||||
flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
|
||||
flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
|
||||
{Adr1E, Adr2E, Adr3E});
|
||||
flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD},
|
||||
{FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE});
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
//EXECUTION STAGE
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// Hazard unit for FPU
|
||||
// - determines if any forwarding or stalls are needed
|
||||
fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResultSelM,
|
||||
// outputs:
|
||||
.FStallD, .FForwardXE, .FForwardYE, .FForwardZE);
|
||||
|
||||
|
||||
// forwarding muxs
|
||||
mux3 #(64) fxemux(FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
|
||||
mux3 #(64) fyemux(FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
|
||||
mux3 #(64) fzemux(FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
|
||||
mux3 #(64) fyaddmux(FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0}, {2'b0, {10{1'b1}}, 52'b0}, {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==3'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==3'b01)}, FSrcYE); // Force Z to be 0 for multiply instructions
|
||||
mux3 #(64) fzmulmux(FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); // Force Z to be 0 for multiply instructions
|
||||
|
||||
|
||||
// unpacking unit
|
||||
// - splits FP inputs into their various parts
|
||||
// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
|
||||
unpacking unpacking(.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE,
|
||||
// outputs:
|
||||
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
|
||||
.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
|
||||
|
||||
// FMA
|
||||
// - two stage FMA
|
||||
// - execute stage - multiplication and addend shifting
|
||||
// - memory stage - addition and rounding
|
||||
// - handles FMA and multiply instructions
|
||||
// - contains some E/M pipleine registers
|
||||
// *** currently handles FLEN and 32 bits(dont know if 32 works with 128 - easy to fix) - change to handle only the supported formats
|
||||
fma fma (.clk, .reset, .FlushM, .StallM,
|
||||
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE,
|
||||
.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
|
||||
.XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM,
|
||||
.XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
|
||||
.FOpCtrlE,
|
||||
.FmtE, .FmtM, .FrmM,
|
||||
// outputs:
|
||||
.FMAFlgM, .FMAResM);
|
||||
|
||||
// clock gater
|
||||
// - creates a clock that only runs durring divide/sqrt instructions
|
||||
// - using the seperate clock gives the divide/sqrt unit some to get set up
|
||||
// *** the module says not to use in synthisis
|
||||
clockgater fpdivclkg(.E(FDivStartE),
|
||||
.SE(1'b0),
|
||||
.CLK(clk),
|
||||
.ECLK(FDivClk));
|
||||
|
||||
// capture the inputs for divide/sqrt
|
||||
// - if not captured any forwarded inputs will change durring computation
|
||||
// - this problem is caused by stalling the execute stage
|
||||
// - the other units don't have this problem, only div/sqrt stalls the execute stage
|
||||
flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
|
||||
.en(1'b1), .clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(FDivBusyE));
|
||||
flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
|
||||
.en(1'b1), .clear(FDivSqrtDoneE),
|
||||
.reset(reset), .clk(FDivBusyE));
|
||||
|
||||
// output for store instructions
|
||||
//*** change to use the unpacking unit if possible
|
||||
fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
|
||||
.reset, .clk(FDivClk), .start(FDivStartE), .P(~FmtE), .OvEn(1'b1), .UnEn(1'b1),
|
||||
// outputs:
|
||||
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
|
||||
|
||||
// convert from signle to double and vice versa
|
||||
cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
|
||||
|
||||
// compare unit
|
||||
// - computation is done in one stage
|
||||
// - writes to FP file durring min/max instructions
|
||||
// - other comparisons write a 1 or 0 to the integer register
|
||||
fcmp fcmp (.op1({XSgnE,XExpE,XManE[`NF-1:0]}), .op2({YSgnE,YExpE,YManE[`NF-1:0]}),
|
||||
.FSrcXE, .FSrcYE, .FOpCtrlE,
|
||||
.FmtE, .XNaNE, .YNaNE, .XZeroE, .YZeroE,
|
||||
// outputs:
|
||||
.Invalid(CmpNVE), .CmpResE);
|
||||
|
||||
// sign injection unit
|
||||
// - computation is done in one stage
|
||||
fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE,
|
||||
// outputs:
|
||||
.SgnNVE, .SgnResE);
|
||||
|
||||
// classify
|
||||
// - computation is done in one stage
|
||||
// - most of the work is done in the unpacking unit
|
||||
// - result is written to the integer register
|
||||
fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE,
|
||||
// outputs:
|
||||
.XSNaNE, .ClassResE);
|
||||
|
||||
fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE,
|
||||
// outputs:
|
||||
.CvtResE, .CvtFlgE);
|
||||
|
||||
// data to be stored in memory - to IEU
|
||||
// - FP uses NaN-blocking format
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
assign FWriteDataE = FSrcYE[`XLEN-1:0];
|
||||
|
||||
|
||||
// Align SrcA to MSB when single precicion
|
||||
mux2 #(64) SrcAMux({{32{1'b1}}, SrcAE[31:0]}, {{64-`XLEN{1'b1}}, SrcAE}, FmtE, AlignedSrcAE);
|
||||
|
||||
// select a result that may be written to the FP register
|
||||
mux5 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE);
|
||||
mux5 #(5) FFlgMux(5'b0, {4'b0, SgnNVE}, {4'b0, CmpNVE}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE);
|
||||
|
||||
// select the result that may be written to the integer register - to IEU
|
||||
mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], CvtResE[`XLEN-1:0], FIntResSelE, FIntResE);
|
||||
|
||||
|
||||
|
||||
//***will synth remove registers of values that are always zero?
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
// E/M pipe registers
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM);
|
||||
flopenrc #(65) EMFpReg2(clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM});
|
||||
flopenrc #(65) EMFpReg3(clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM});
|
||||
flopenrc #(64) EMFpReg4(clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
|
||||
flopenrc #(12) EMFpReg5(clk, reset, FlushM, ~StallM,
|
||||
{XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
|
||||
{XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
|
||||
|
||||
flopenrc #(64) EMRegCmpRes(clk, reset, FlushM, ~StallM, FResE, FResM);
|
||||
flopenrc #(5) EMRegCmpFlg(clk, reset, FlushM, ~StallM, FFlgE, FFlgM);
|
||||
|
||||
flopenrc #(`XLEN) EMRegSgnRes(clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
|
||||
// flopenrc #(1) EMRegSgnFlg(clk, reset, FlushM, ~StallM, SgnNVE, SgnNVM);
|
||||
|
||||
//flopenrc #(64) EMRegCvtFpRes(clk, reset, FlushM, ~StallM, CvtFpResE, CvtFpResM);
|
||||
//flopenrc #(5) EMRegCvtFpFlg(clk, reset, FlushM, ~StallM, CvtFpFlgE, CvtFpFlgM);
|
||||
|
||||
// flopenrc #(64) EMRegCvtRes(clk, reset, FlushM, ~StallM, CvtResE, CvtResM);
|
||||
// flopenrc #(5) EMRegCvtFlg(clk, reset, FlushM, ~StallM, CvtFlgE, CvtFlgM);
|
||||
|
||||
// flopenrc #(64) EMRegClass(clk, reset, FlushM, ~StallM, ClassResE, ClassResM);
|
||||
|
||||
flopenrc #(11) EMCtrlReg(clk, reset, FlushM, ~StallM,
|
||||
{FRegWriteE, FResultSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE},
|
||||
{FRegWriteM, FResultSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM});
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
//BEGIN MEMORY STAGE
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// FPU flag selection - to privileged
|
||||
mux4 #(5) FPUFlgMux(5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
// M/W pipe registers
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
|
||||
flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW);
|
||||
flopenrc #(64) MWRegAdd(clk, reset, FlushW, ~StallW, CvtFpResM, CvtFpResW);
|
||||
flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
|
||||
flopenrc #(5) MWCtrlReg(clk, reset, FlushW, ~StallW,
|
||||
{FRegWriteM, FResultSelM, FmtM, FWriteIntM},
|
||||
{FRegWriteW, FResultSelW, FmtW, FWriteIntW});
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN WRITEBACK STAGE
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// put ReadData into NaN-blocking format
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
// - for load instruction
|
||||
mux2 #(64) ReadResMux({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
|
||||
|
||||
// select the result to be written to the FP register
|
||||
mux4 #(64) FPUResultMux(ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW);
|
||||
|
||||
|
||||
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
||||
assign FStallD = 0;
|
||||
assign FWriteIntE = 0;
|
||||
assign FWriteIntM = 0;
|
||||
assign FWriteIntW = 0;
|
||||
assign FWriteDataE = 0;
|
||||
assign FIntResM = 0;
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrD = 1;
|
||||
assign SetFflagsM = 0;
|
||||
assign FStallD = 0;
|
||||
assign FWriteIntE = 0;
|
||||
assign FWriteIntM = 0;
|
||||
assign FWriteIntW = 0;
|
||||
assign FWriteDataE = 0;
|
||||
assign FIntResM = 0;
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrD = 1;
|
||||
assign SetFflagsM = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
@ -1,10 +1,9 @@
|
||||
///////////////////////////////////////////
|
||||
// regfile.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
// Modified: James Stine
|
||||
//
|
||||
// Purpose: 4-port register file
|
||||
// Purpose: 3-port output register file
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
@ -26,22 +25,20 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fregfile (
|
||||
input logic clk, reset,
|
||||
input logic we4,
|
||||
input logic [ 4:0] a1, a2, a3, a4,
|
||||
input logic [63:0] wd4,
|
||||
input logic clk, reset,
|
||||
input logic we4,
|
||||
input logic [4:0] a1, a2, a3, a4,
|
||||
input logic [63:0] wd4,
|
||||
output logic [63:0] rd1, rd2, rd3);
|
||||
|
||||
logic [63:0] rf[31:0];
|
||||
integer i;
|
||||
|
||||
// three ported register file
|
||||
// read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
|
||||
// write fourth port on rising edge of clock (A4/WD4/WE4)
|
||||
// write occurs on falling edge of clock
|
||||
|
||||
// reset is intended for simulation only, not synthesis
|
||||
|
||||
|
||||
logic [63:0] rf[31:0];
|
||||
integer i;
|
||||
|
||||
// three ported register file
|
||||
// read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
|
||||
// write fourth port on rising edge of clock (A4/WD4/WE4)
|
||||
// write occurs on falling edge of clock
|
||||
|
||||
always_ff @(negedge clk or posedge reset)
|
||||
if (reset) for(i=0; i<32; i++) rf[i] <= 0;
|
||||
else if (we4) rf[a4] <= wd4;
|
||||
|
@ -1,62 +1,63 @@
|
||||
module fsm (
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 9/28/2021
|
||||
//
|
||||
// Purpose: FSM for floating point divider/square root unit (Goldschmidt)
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
input logic op_type,
|
||||
output logic done, // End of cycles
|
||||
output logic load_rega, // enable for regA
|
||||
output logic load_regb, // enable for regB
|
||||
output logic load_regc, // enable for regC
|
||||
output logic load_regd, // enable for regD
|
||||
output logic load_regr, // enable for rem
|
||||
output logic load_regs, // enable for q,qm,qp
|
||||
output logic [2:0] sel_muxa, // Select muxA
|
||||
output logic [2:0] sel_muxb, // Select muxB
|
||||
output logic sel_muxr, // Select rem mux
|
||||
output logic divBusy // calculation is happening
|
||||
module fsm (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
input logic op_type,
|
||||
output logic done,
|
||||
output logic load_rega,
|
||||
output logic load_regb,
|
||||
output logic load_regc,
|
||||
output logic load_regd,
|
||||
output logic load_regr,
|
||||
output logic load_regs,
|
||||
output logic [2:0] sel_muxa,
|
||||
output logic [2:0] sel_muxb,
|
||||
output logic sel_muxr,
|
||||
output logic divBusy
|
||||
);
|
||||
|
||||
|
||||
reg [4:0] CURRENT_STATE;
|
||||
reg [4:0] NEXT_STATE;
|
||||
|
||||
parameter [4:0]
|
||||
S0=5'd0, S1=5'd1, S2=5'd2,
|
||||
S3=5'd3, S4=5'd4, S5=5'd5,
|
||||
S6=5'd6, S7=5'd7, S8=5'd8,
|
||||
S9=5'd9, S10=5'd10,
|
||||
S13=5'd13, S14=5'd14, S15=5'd15,
|
||||
S16=5'd16, S17=5'd17, S18=5'd18,
|
||||
S19=5'd19, S20=5'd20, S21=5'd21,
|
||||
S22=5'd22, S23=5'd23, S24=5'd24,
|
||||
S25=5'd25, S26=5'd26, S27=5'd27,
|
||||
S28=5'd28, S29=5'd29, S30=5'd30;
|
||||
typedef enum logic [4:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9,
|
||||
S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
|
||||
S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
|
||||
S30} statetype;
|
||||
|
||||
statetype current_state, next_state;
|
||||
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if(reset==1'b1)
|
||||
CURRENT_STATE=S0;
|
||||
if (reset == 1'b1)
|
||||
current_state = S0;
|
||||
else
|
||||
CURRENT_STATE=NEXT_STATE;
|
||||
current_state = next_state;
|
||||
end
|
||||
|
||||
always_comb
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b0;
|
||||
load_rega = 1'b0;
|
||||
load_regb = 1'b0;
|
||||
load_regc = 1'b0;
|
||||
load_regd = 1'b0;
|
||||
load_regr = 1'b0;
|
||||
load_regs = 1'b0;
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S0;
|
||||
|
||||
case(CURRENT_STATE)
|
||||
case(current_state)
|
||||
S0: // iteration 0
|
||||
begin
|
||||
if (start==1'b0)
|
||||
@ -72,7 +73,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S0;
|
||||
next_state = S0;
|
||||
end
|
||||
else if (start==1'b1 && op_type==1'b0)
|
||||
begin
|
||||
@ -87,7 +88,7 @@ module fsm (
|
||||
sel_muxa = 3'b001;
|
||||
sel_muxb = 3'b001;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S1;
|
||||
next_state = S1;
|
||||
end // if (start==1'b1 && op_type==1'b0)
|
||||
else if (start==1'b1 && op_type==1'b1)
|
||||
begin
|
||||
@ -102,7 +103,7 @@ module fsm (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S13;
|
||||
next_state = S13;
|
||||
end
|
||||
else
|
||||
begin
|
||||
@ -117,7 +118,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S0;
|
||||
next_state = S0;
|
||||
end
|
||||
end // case: S0
|
||||
S1:
|
||||
@ -133,7 +134,7 @@ module fsm (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S2;
|
||||
next_state = S2;
|
||||
end
|
||||
S2: // iteration 1
|
||||
begin
|
||||
@ -148,7 +149,7 @@ module fsm (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S3;
|
||||
next_state = S3;
|
||||
end
|
||||
S3:
|
||||
begin
|
||||
@ -163,7 +164,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S4;
|
||||
next_state = S4;
|
||||
end
|
||||
S4: // iteration 2
|
||||
begin
|
||||
@ -178,7 +179,7 @@ module fsm (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S5;
|
||||
next_state = S5;
|
||||
end
|
||||
S5:
|
||||
begin
|
||||
@ -193,7 +194,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0; // add
|
||||
NEXT_STATE = S6;
|
||||
next_state = S6;
|
||||
end
|
||||
S6: // iteration 3
|
||||
begin
|
||||
@ -208,7 +209,7 @@ module fsm (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S8;
|
||||
next_state = S8;
|
||||
end
|
||||
S7:
|
||||
begin
|
||||
@ -223,7 +224,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S8;
|
||||
next_state = S8;
|
||||
end // case: S7
|
||||
S8: // q,qm,qp
|
||||
begin
|
||||
@ -238,7 +239,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S9;
|
||||
next_state = S9;
|
||||
end
|
||||
S9: // rem
|
||||
begin
|
||||
@ -253,7 +254,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b1;
|
||||
NEXT_STATE = S10;
|
||||
next_state = S10;
|
||||
end
|
||||
S10: // done
|
||||
begin
|
||||
@ -268,7 +269,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S0;
|
||||
next_state = S0;
|
||||
end
|
||||
S13: // start of sqrt path
|
||||
begin
|
||||
@ -283,7 +284,7 @@ module fsm (
|
||||
sel_muxa = 3'b010;
|
||||
sel_muxb = 3'b001;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S14;
|
||||
next_state = S14;
|
||||
end
|
||||
S14:
|
||||
begin
|
||||
@ -298,7 +299,7 @@ module fsm (
|
||||
sel_muxa = 3'b001;
|
||||
sel_muxb = 3'b100;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S15;
|
||||
next_state = S15;
|
||||
end
|
||||
S15: // iteration 1
|
||||
begin
|
||||
@ -313,7 +314,7 @@ module fsm (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S16;
|
||||
next_state = S16;
|
||||
end
|
||||
S16:
|
||||
begin
|
||||
@ -328,7 +329,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S17;
|
||||
next_state = S17;
|
||||
end
|
||||
S17:
|
||||
begin
|
||||
@ -343,7 +344,7 @@ module fsm (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S18;
|
||||
next_state = S18;
|
||||
end
|
||||
S18: // iteration 2
|
||||
begin
|
||||
@ -358,7 +359,7 @@ module fsm (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S19;
|
||||
next_state = S19;
|
||||
end
|
||||
S19:
|
||||
begin
|
||||
@ -373,7 +374,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S20;
|
||||
next_state = S20;
|
||||
end
|
||||
S20:
|
||||
begin
|
||||
@ -388,7 +389,7 @@ module fsm (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S21;
|
||||
next_state = S21;
|
||||
end
|
||||
S21: // iteration 3
|
||||
begin
|
||||
@ -403,7 +404,7 @@ module fsm (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S22;
|
||||
next_state = S22;
|
||||
end
|
||||
S22:
|
||||
begin
|
||||
@ -418,7 +419,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b011;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S23;
|
||||
next_state = S23;
|
||||
end
|
||||
S23:
|
||||
begin
|
||||
@ -433,7 +434,7 @@ module fsm (
|
||||
sel_muxa = 3'b100;
|
||||
sel_muxb = 3'b010;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S24;
|
||||
next_state = S24;
|
||||
end
|
||||
S24: // q,qm,qp
|
||||
begin
|
||||
@ -448,7 +449,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S25;
|
||||
next_state = S25;
|
||||
end
|
||||
S25: // rem
|
||||
begin
|
||||
@ -463,7 +464,7 @@ module fsm (
|
||||
sel_muxa = 3'b011;
|
||||
sel_muxb = 3'b110;
|
||||
sel_muxr = 1'b1;
|
||||
NEXT_STATE = S26;
|
||||
next_state = S26;
|
||||
end
|
||||
S26: // done
|
||||
begin
|
||||
@ -478,7 +479,7 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S0;
|
||||
next_state = S0;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
@ -493,9 +494,9 @@ module fsm (
|
||||
sel_muxa = 3'b000;
|
||||
sel_muxb = 3'b000;
|
||||
sel_muxr = 1'b0;
|
||||
NEXT_STATE = S0;
|
||||
next_state = S0;
|
||||
end
|
||||
endcase // case(CURRENT_STATE)
|
||||
end // always @ (CURRENT_STATE or X)
|
||||
endcase // case(current_state)
|
||||
end // always @ (current_state or X)
|
||||
|
||||
endmodule // fsm
|
||||
|
@ -1,37 +1,55 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// The rounder takes as inputs a 64-bit value to be rounded, A, the
|
||||
// exponent of the value to be rounded, the sign of the final result, Sign,
|
||||
// the precision of the results, P, and the two-bit rounding mode, rm.
|
||||
// It produces a rounded 52-bit result, Z, the exponent of the rounded
|
||||
// result, Z_exp, and a flag that indicates if the result was rounded,
|
||||
// Inexact. The rounding mode has the following values.
|
||||
// rm Mode
|
||||
// 00 round-to-nearest-even
|
||||
// 01 round-toward-zero
|
||||
// 10 round-toward-plus infinity
|
||||
// 11 round-toward-minus infinity
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Floating point divider/square root rounder unit (Goldschmidt)
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module rounder_div (
|
||||
input logic [1:0] rm,
|
||||
input logic P,
|
||||
input logic OvEn,
|
||||
input logic UnEn,
|
||||
input logic [12:0] exp_diff,
|
||||
input logic [2:0] sel_inv,
|
||||
input logic Invalid,
|
||||
input logic SignR,
|
||||
|
||||
input logic [63:0] q1,
|
||||
input logic [63:0] qm1,
|
||||
input logic [63:0] qp1,
|
||||
input logic [63:0] q0,
|
||||
input logic [63:0] qm0,
|
||||
input logic [63:0] qp0,
|
||||
input logic [1:0] rm,
|
||||
input logic P,
|
||||
input logic OvEn,
|
||||
input logic UnEn,
|
||||
input logic [12:0] exp_diff,
|
||||
input logic [2:0] sel_inv,
|
||||
input logic Invalid,
|
||||
input logic SignR,
|
||||
input logic [63:0] Float1,
|
||||
input logic [63:0] Float2,
|
||||
input logic XNaNQ,
|
||||
input logic YNaNQ,
|
||||
input logic XZeroQ,
|
||||
input logic YZeroQ,
|
||||
input logic XInfQ,
|
||||
input logic YInfQ,
|
||||
input logic op_type,
|
||||
input logic [63:0] q1,
|
||||
input logic [63:0] qm1,
|
||||
input logic [63:0] qp1,
|
||||
input logic [63:0] q0,
|
||||
input logic [63:0] qm0,
|
||||
input logic [63:0] qp0,
|
||||
input logic [127:0] regr_out,
|
||||
|
||||
output logic [63:0] Result,
|
||||
output logic [4:0] Flags
|
||||
output logic [4:0] Flags
|
||||
);
|
||||
|
||||
logic Rsign;
|
||||
@ -56,11 +74,15 @@ module rounder_div (
|
||||
logic Texp_l7z;
|
||||
logic Texp_l7o;
|
||||
logic OvCon;
|
||||
logic zero_rem;
|
||||
logic [1:0] mux_mant;
|
||||
logic zero_rem;
|
||||
logic [1:0] mux_mant;
|
||||
logic sign_rem;
|
||||
logic [63:0] q, qm, qp;
|
||||
logic exp_ovf;
|
||||
logic [63:0] q, qm, qp;
|
||||
logic exp_ovf;
|
||||
|
||||
logic [50:0] NaN_out;
|
||||
logic NaN_Sign_out;
|
||||
logic Sign_out;
|
||||
|
||||
// Remainder = 0?
|
||||
assign zero_rem = ~(|regr_out);
|
||||
@ -117,12 +139,11 @@ module rounder_div (
|
||||
// the input was infinite or NaN or the output of the adder is zero.
|
||||
// 00 = Valid
|
||||
// 10 = NaN
|
||||
assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]);
|
||||
assign NaN = ~sel_inv[1]& sel_inv[0];
|
||||
assign Valid = ~sel_inv[2]&~sel_inv[1]&~sel_inv[0];
|
||||
assign NaN = sel_inv[2]&sel_inv[1]&sel_inv[0];
|
||||
assign UnderFlow = (P & UnFlow_SP | UnFlow_DP) & Valid;
|
||||
assign OverFlow = (P & OvFlow_SP | OvFlow_DP) & Valid;
|
||||
assign Div0 = sel_inv[2]&sel_inv[1]&~sel_inv[0];
|
||||
|
||||
assign Div0 = YZeroQ&~XZeroQ&~op_type&~NaN;
|
||||
|
||||
// The final result is Inexact if any rounding occurred ((i.e., R or S
|
||||
// is one), or (if the result overflows ) or (if the result underflows and the
|
||||
@ -161,18 +182,26 @@ module rounder_div (
|
||||
// If the result is zero or infinity, the mantissa is all zeros.
|
||||
// If the result is NaN, the mantissa is 10...0
|
||||
// If the result the largest floating point number, the mantissa
|
||||
// is all ones. Otherwise, the mantissa is not changed.
|
||||
assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero);
|
||||
assign Rmant[50:0] = {51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}});
|
||||
// is all ones. Otherwise, the mantissa is not changed.
|
||||
assign NaN_out = ~XNaNQ&YNaNQ ? Float2[50:0] : Float1[50:0];
|
||||
assign NaN_Sign_out = ~XNaNQ&YNaNQ ? Float2[63] : Float1[63];
|
||||
assign Sign_out = (XZeroQ&YZeroQ | XInfQ&YInfQ)&~op_type | Rsign&~XNaNQ&~YNaNQ |
|
||||
NaN_Sign_out&(XNaNQ|YNaNQ);
|
||||
|
||||
// FIXME (jes) - Imperas gives sNaN a Sign=0 where x86 gives Sign=1
|
||||
// | Float1[63]&op_type;
|
||||
assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero);
|
||||
assign Rmant[50:0] = ({51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}}) |
|
||||
(NaN_out&{51{NaN}}))&({51{~(op_type&Float1[63]&~XZeroQ)}});
|
||||
|
||||
// For single precision, the 8 least significant bits of the exponent
|
||||
// and 23 most significant bits of the mantissa contain bits used
|
||||
// for the final result. A double precision result is returned if
|
||||
// overflow has occurred, the overflow trap is enabled, and a conversion
|
||||
// is being performed.
|
||||
assign OvCon = OverFlow & OvEn;
|
||||
assign Result = (P&~OvCon) ? { {32{1'b1}}, Rsign, Rexp[7:0], Rmant[51:29]}
|
||||
: {Rsign, Rexp, Rmant};
|
||||
assign Result = (P&~OvCon) ? { {32{1'b1}}, Sign_out, Rexp[7:0], Rmant[51:29]}
|
||||
: {Sign_out, Rexp, Rmant};
|
||||
|
||||
endmodule // rounder
|
||||
|
||||
|
@ -1,5 +1,30 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Bipartite Lookup
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module sbtm_a0 (input logic [6:0] a,
|
||||
output logic [12:0] y);
|
||||
output logic [12:0] y);
|
||||
|
||||
always_comb
|
||||
case(a)
|
||||
7'b0000000: y = 13'b1111111100010;
|
||||
@ -137,4 +162,4 @@ endmodule // sbtm_a0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
@ -1,5 +1,30 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Bipartite Lookup
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module sbtm_a1 (input logic [6:0] a,
|
||||
output logic [4:0] y);
|
||||
output logic [4:0] y);
|
||||
|
||||
always_comb
|
||||
case(a)
|
||||
7'b0000000: y = 5'b11100;
|
||||
@ -137,4 +162,4 @@ endmodule // sbtm_a0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
@ -1,5 +1,30 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Bipartite Lookup
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module sbtm_a2 (input logic [7:0] a,
|
||||
output logic [13:0] y);
|
||||
output logic [13:0] y);
|
||||
|
||||
always_comb
|
||||
case(a)
|
||||
8'b01000000: y = 14'b10110100010111;
|
||||
@ -201,4 +226,4 @@ endmodule // sbtm_a0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
@ -1,5 +1,30 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Bipartite Lookup
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module sbtm_a3 (input logic [7:0] a,
|
||||
output logic [5:0] y);
|
||||
output logic [5:0] y);
|
||||
|
||||
always_comb
|
||||
case(a)
|
||||
8'b01000000: y = 6'b100110;
|
||||
|
@ -1,3 +1,27 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Bipartite Lookup for divide portion of fpdivsqrt
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module sbtm_div (input logic [11:0] a, output logic [10:0] ia_out);
|
||||
|
||||
// bit partitions
|
||||
|
@ -1,3 +1,27 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// Written: James Stine
|
||||
// Modified: 8/1/2018
|
||||
//
|
||||
// Purpose: Bipartite Lookup for sqrt part of fpdivsqrt
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module sbtm_sqrt (input logic [11:0] a, output logic [10:0] y);
|
||||
|
||||
// bit partitions
|
||||
|
35
wally-pipelined/src/generic/adder.sv
Normal file
35
wally-pipelined/src/generic/adder.sv
Normal file
@ -0,0 +1,35 @@
|
||||
///////////////////////////////////////////
|
||||
// adder.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 2 October 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Adder
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module adder #(parameter WIDTH=8) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
|
||||
|
38
wally-pipelined/src/generic/counter.sv
Normal file
38
wally-pipelined/src/generic/counter.sv
Normal file
@ -0,0 +1,38 @@
|
||||
///////////////////////////////////////////
|
||||
// counter.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 10 October 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Counter with reset and enable
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module counter #(parameter WIDTH=8) (
|
||||
input logic clk, reset, en,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
logic [WIDTH-1:0] qnext;
|
||||
|
||||
assign qnext = q + 1;
|
||||
flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
|
||||
endmodule
|
||||
|
||||
|
34
wally-pipelined/src/generic/neg.sv
Normal file
34
wally-pipelined/src/generic/neg.sv
Normal file
@ -0,0 +1,34 @@
|
||||
///////////////////////////////////////////
|
||||
// neg.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 28 September 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: 2's complement negator
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module neg #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = ~a + 1;
|
||||
endmodule
|
||||
|
@ -30,9 +30,10 @@ module forward(
|
||||
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
|
||||
input logic MemReadE, MulDivE, CSRReadE,
|
||||
input logic RegWriteM, RegWriteW,
|
||||
input logic DivDoneE, DivBusyE,
|
||||
input logic DivBusyE,
|
||||
input logic FWriteIntE, FWriteIntM, FWriteIntW,
|
||||
input logic SCE,
|
||||
input logic StallD,
|
||||
// Forwarding controls
|
||||
output logic [1:0] ForwardAE, ForwardBE,
|
||||
output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD
|
||||
@ -53,7 +54,7 @@ module forward(
|
||||
// Stall on dependent operations that finish in Mem Stage and can't bypass in time
|
||||
assign FPUStallD = FWriteIntE & ((Rs1D == RdE) | (Rs2D == RdE));
|
||||
assign LoadStallD = (MemReadE|SCE) & ((Rs1D == RdE) | (Rs2D == RdE));
|
||||
assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE | DivBusyE; // *** extend with stalls for divide
|
||||
assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE));
|
||||
assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE));
|
||||
|
||||
endmodule
|
||||
|
@ -73,7 +73,6 @@ module ieu (
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD,
|
||||
output logic PCSrcE,
|
||||
input logic DivDoneE,
|
||||
input logic DivBusyE,
|
||||
output logic CSRReadM, CSRWriteM, PrivilegedM,
|
||||
output logic CSRWritePendingDEM,
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user