James E. Stine 2afa6e7a6e Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included		2021-10-06 08:56:01 -05:00
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common	SRT Division unsigned passing Imperas tests	2021-09-30 12:17:24 -04:00
fp	Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included	2021-10-06 08:56:01 -05:00
imperas-boottim.txt	added sfence to legal instructions, zeroed out rom file to populate for tests	2021-07-23 15:55:08 -04:00
testbench-arch.sv	Divide performs 2 steps per cycle	2021-10-02 09:19:25 -04:00
testbench-coremark_bare.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-coremark.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-fpga.sv	FPGA test bench and test program.	2021-09-12 20:41:54 -05:00
testbench-imperas.sv	Reduced cycle count for DIVW/DIVUW by two	2021-10-03 09:42:22 -04:00
testbench-linux.sv	added delayed MIP signal	2021-10-04 18:23:31 -04:00
testbench-privileged.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00