David Harris
9f24b4c969
Simplified performance counters
2021-12-31 06:40:21 +00:00
David Harris
42df98bc6d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 23:40:02 +00:00
David Harris
b96439dd73
Fixes to counters; buildroot still broken
2021-12-30 23:39:59 +00:00
Ross Thompson
6b59c03d1b
No dcache now supported. Does not pass regression tests however.
2021-12-30 15:26:32 -06:00
David Harris
2327f4b6bf
Added names to generate blocks
2021-12-30 20:55:48 +00:00
David Harris
d7653dedee
Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
2021-12-30 17:22:18 +00:00
Ross Thompson
077bc35e10
Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
2021-12-29 22:24:37 -06:00
David Harris
c54d81ab04
Fixed generate statement name in csrm for buildroot regression
2021-12-30 03:01:21 +00:00
David Harris
d8ba97cf71
RV32ic tests running for simple machine with no privileged unit
2021-12-30 02:25:46 +00:00
David Harris
98aaa970dd
rv32i regression and linting
2021-12-30 00:53:39 +00:00
Ross Thompson
050523487c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
b1116600fe
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
David Harris
52a38c5856
Added performance counting to sumtest and added imperas32/64periph to testbench.
2021-12-29 00:28:51 +00:00
David Harris
6e20d011d5
Fixed imperas C tests
2021-12-26 04:45:06 +00:00
David Harris
e6ed1372a7
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
48bb534658
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
Ross Thompson
50b307bc0e
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
David Harris
a25d541dcf
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
3c3bfd055e
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
d9cc9afd49
Changes to buildroot to support MemAdrM to IEUAdrM name changes.
2021-12-19 18:24:40 -06:00
David Harris
aebd746e71
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
David Harris
2d24230093
ALU and datapath cleanup
2021-12-14 11:15:47 -08:00
David Harris
55f3979b67
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-13 07:57:49 -08:00
David Harris
2039752740
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
Kevin
98420cb988
dot stars conversions on the rest of the testbenches
2021-12-12 17:53:26 -08:00
Kevin
1a82b50483
edited one testbench, yet to run regression
2021-12-10 20:26:20 -08:00
bbracker
f8cffca2b2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 14:12:09 -08:00
bbracker
5feccaec68
fix release of ReadDataM
2021-12-08 14:11:43 -08:00
Ross Thompson
8b7cefab79
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 13:40:44 -06:00
Ross Thompson
9ddd065340
Updated coremark testbench with the extra ports from FPGA merge.
...
Fixed coremark Makefile to create work directory.
2021-12-08 13:40:32 -06:00
bbracker
979580b1e7
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
Skylar Litz
546f7fb4c2
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
500e6ff430
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
b03ca464f1
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
a871118116
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
fed0bb08d6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
bbracker
cffb72042a
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
David Harris
82cfebfb83
Coremark Cleanup, trying compile from addins
2021-11-19 06:09:04 -08:00
David Harris
690410721d
Cleaning up CoreMark benchmark
2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532
vert "Simplifying riscv-coremark"
...
This reverts commit ce8232e396
2021-11-18 18:40:13 -08:00
David Harris
ce8232e396
Simplifying riscv-coremark
2021-11-18 17:15:40 -08:00
David Harris
402b473dbb
CoreMark testing
2021-11-18 16:14:25 -08:00
David Harris
0a281a06e0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:28:33 -08:00
Skylar Litz
6fde97b16c
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
David Harris
c610be25a7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
bbracker
2203590f9f
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Skylar Litz
3dd83b3113
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
