forked from Github_Repos/cvw
adapt testbench linux to use reset_ext
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parent
787b54dffc
commit
66e53929ce
@ -2,6 +2,7 @@ onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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add wave -noupdate -radix unsigned /testbench/InstrCountW
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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@ -509,7 +510,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
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add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
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add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {197 ns} 0}
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WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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@ -48,8 +48,8 @@ module testbench();
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// HARDWARE ///////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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logic clk, reset;
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initial begin reset <= 1; # 22; reset <= 0; end
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logic clk, reset, reset_ext;
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initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
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always begin clk <= 1; # 5; clk <= 0; # 5; end
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logic [`AHBW-1:0] HRDATAEXT;
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@ -69,7 +69,7 @@ module testbench();
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logic UARTSout;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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wallypipelinedsoc dut(.clk, .reset,
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wallypipelinedsoc dut(.clk, .reset_ext, .reset,
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.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR,
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.HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
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.GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
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@ -219,7 +219,9 @@ module testbench();
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initial begin \
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if (CHECKPOINT!=0) begin \
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force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
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#23; \
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while (reset!==1) #1; \
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while (reset!==0) #1; \
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#1; \
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release `SIGNAL; \
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end \
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end
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@ -232,7 +234,9 @@ module testbench();
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initial begin \
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if (CHECKPOINT!=0) begin \
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force `SIGNAL_BASE[i].`SIGNAL = init``SIGNAL[i]; \
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#23; \
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while (reset!==1) #1; \
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while (reset!==0) #1; \
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#1; \
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release `SIGNAL_BASE[i].`SIGNAL; \
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end \
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end \
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@ -245,7 +249,9 @@ module testbench();
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initial begin \
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if (CHECKPOINT!=0) begin \
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force `SIGNAL = init``SIGNAL[0]; \
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#23; \
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while (reset!==1) #1; \
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while (reset!==0) #1; \
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#1; \
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release `SIGNAL; \
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end \
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end
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@ -302,7 +308,9 @@ module testbench();
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force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0];
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force `INSTRET = CHECKPOINT;
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force `CURR_PRIV = initPriv;
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#23;
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while (reset!==1) #1;
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while (reset!==0) #1;
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#1;
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release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV};
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release {`STATUS_FS,`STATUS_MPP};
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release {`STATUS_SPP,`STATUS_MPIE};
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