forked from Github_Repos/cvw
some linux testbench cleanup
This commit is contained in:
bbracker
parent
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commit
9b98a499d7
@ -43,17 +43,23 @@
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`endif
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module testbench();
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///////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////// CONFIG ////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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parameter INSTR_LIMIT = 0; // # of instructions at which to stop
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parameter INSTR_WAVEON = (INSTR_LIMIT > 10000) ? INSTR_LIMIT-10000 : 1; // # of instructions at which to turn on waves in graphical sim
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string ProgramAddrMapFile, ProgramLabelMapFile;
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parameter INSTR_WAVEON = 8.7e6;//(INSTR_LIMIT > 10000) ? INSTR_LIMIT-10000 : 1; // # of instructions at which to turn on waves in graphical sim
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//parameter CHECKPOINT = 0;
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////// DUT /////////////////////////////////////
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////////////////////////////////// HARDWARE ///////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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logic clk, reset;
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logic [`AHBW-1:0] readDataExpected;
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logic clk, reset;
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initial begin reset <= 1; # 22; reset <= 0; end
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always begin clk <= 1; # 5; clk <= 0; # 5; end
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic HCLK, HRESETn;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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@ -62,50 +68,44 @@ module testbench();
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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logic UARTSin;
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logic UARTSout;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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wallypipelinedsoc dut(.clk, .reset,
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.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR,
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.HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
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.GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
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.UARTSin, .UARTSout);
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wallypipelinedsoc dut(.*);
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// Write Back stage signals not needed by Wally itself
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logic [`XLEN-1:0] PCW;
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logic [31:0] InstrW;
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logic InstrValidW;
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logic [`XLEN-1:0] MemAdrW, WriteDataW;
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logic TrapW;
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`define FLUSHW dut.hart.FlushW
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`define STALLW dut.hart.StallW
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flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
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flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
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flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
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flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);
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flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////// Signals & Shared Macros ///////////////////////////
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//////////////////////// AKA stuff that comes first ///////////////////////////
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//////////////////////// Signals & Macro DECLARATIONS /////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Sorry if these have gotten decontextualized.
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// Verilog expects them to be defined before they are used.
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// -------------------
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// Signal Declarations
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// -------------------
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// Testbench Core
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integer warningCount = 0;
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integer errorCount = 0;
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integer MIPexpected;
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// P, Instr Checking
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integer data_file_all;
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string name;
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// Write Back stage signals needed for trace compare, but don't actually
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// exist in CPU.
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logic [`XLEN-1:0] MemAdrW, WriteDataW;
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logic [`XLEN-1:0] PCW;
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logic [31:0] InstrW;
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logic InstrValidW;
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// Write Back trace signals
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logic checkInstrW;
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integer fault;
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logic TrapW;
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// Signals used to parse the trace file.
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logic checkInstrM;
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integer fault;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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// Signals used to parse the trace file
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integer data_file_all;
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string name;
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integer matchCount;
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string line;
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logic [`XLEN-1:0] ExpectedPCM;
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@ -118,8 +118,9 @@ module testbench();
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integer TokenIndex;
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integer MarkerIndex;
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integer NumCSRM;
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// Memory stage expected values from trace
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logic checkInstrM;
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integer MIPexpected;
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string RegWriteM;
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integer ExpectedRegAdrM;
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logic [`XLEN-1:0] ExpectedRegValueM;
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@ -127,8 +128,9 @@ module testbench();
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logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM;
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string ExpectedCSRArrayM[10:0];
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logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0];
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logic [`AHBW-1:0] readDataExpected;
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// Write back stage expected values from trace
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logic checkInstrW;
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logic [`XLEN-1:0] ExpectedPCW;
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logic [31:0] ExpectedInstrW;
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string textW;
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@ -147,26 +149,75 @@ module testbench();
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integer NumCSRPostWIndex;
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logic [`XLEN-1:0] InstrCountW;
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integer RequestDelayedMIP;
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// ------
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// Macros
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// ------
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`define CSRwarn(CSR) \
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// Useful Aliases
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`define RF dut.hart.ieu.dp.regf.rf
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`define PC dut.hart.ifu.pcreg.q
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`define CSR_BASE dut.hart.priv.csr.genblk1
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`define HPMCOUNTER `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
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`define PMP_BASE `CSR_BASE.csrm.genblk4
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`define PMPCFG genblk2.PMPCFGreg.q
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`define PMPADDR PMPADDRreg.q
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`define MEDELEG `CSR_BASE.csrm.genblk1.MEDELEGreg.q
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`define MIDELEG `CSR_BASE.csrm.genblk1.MIDELEGreg.q
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`define MIE `CSR_BASE.csri.MIE_REGW
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`define MIP `CSR_BASE.csri.MIP_REGW
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`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
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`define SCAUSE `CSR_BASE.csrs.genblk1.SCAUSEreg.q
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`define MEPC `CSR_BASE.csrm.MEPCreg.q
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`define SEPC `CSR_BASE.csrs.genblk1.SEPCreg.q
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`define MCOUNTEREN `CSR_BASE.csrm.genblk3.MCOUNTERENreg.q
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`define SCOUNTEREN `CSR_BASE.csrs.genblk1.genblk3.SCOUNTERENreg.q
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`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
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`define SSCRATCH `CSR_BASE.csrs.genblk1.SSCRATCHreg.q
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`define MTVEC `CSR_BASE.csrm.MTVECreg.q
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`define STVEC `CSR_BASE.csrs.genblk1.STVECreg.q
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`define SATP `CSR_BASE.csrs.genblk1.genblk2.SATPreg.q
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`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
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`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
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`define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT
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`define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT
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`define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT
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`define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT
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`define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT
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`define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT
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`define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP
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`define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP
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`define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE
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`define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE
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`define STATUS_UPIE `CSR_BASE.csrsr.STATUS_UPIE
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`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
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`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
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`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
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`define CURR_PRIV dut.hart.priv.privmodereg.q
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`define INSTRET dut.hart.priv.csr.genblk1.counters.genblk1.genblk2.INSTRETreg.q
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// Common Macros
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`define checkCSR(CSR) \
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begin \
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
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if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
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$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
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if(`DEBUG_TRACE >= 3) fault = 1; \
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end \
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end
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`define checkEQ(NAME, VAL, EXPECTED) \
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if(VAL != EXPECTED) begin \
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$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \
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if ((NAME == "PCW") || (`DEBUG_TRACE >= 2)) fault = 1; \
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end
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///////////////////////////////////////////////////////////////////////////////
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/////////////////////////////// INITIALIZATION ////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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initial begin
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$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
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`ifdef CHECKPOINT
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$readmemh({`CHECKPOINT_DIR,"ram.txt"}, dut.uncore.dtim.RAM);
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`else
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$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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`endif
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
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ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
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ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
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`ifdef CHECKPOINT
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data_file_all = $fopen({`CHECKPOINT_DIR,"all.txt"}, "r");
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`else
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@ -182,19 +233,9 @@ module testbench();
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force dut.hart.priv.ExtIntM = 0;
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end
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
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// Additonal W stage registers
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`define FLUSHW dut.hart.FlushW
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`define STALLW dut.hart.StallW
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flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
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flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
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flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);
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flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
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flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
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flopenrc #(5) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////// CORE /////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Because qemu does not match exactly to wally it is necessary to read the the
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// trace in the memory stage and detect if anything in wally must be overwritten.
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// This includes mtimer, interrupts, and various bits in mstatus and xtval.
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@ -203,6 +244,7 @@ module testbench();
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// on the next falling edge the expected state is compared to the wally state.
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// step 0: read the expected state
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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always @(negedge clk) begin
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// always check PC, instruction bits
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if (checkInstrM) begin
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@ -352,6 +394,7 @@ module testbench();
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end
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// step2: make all checks in the write back stage.
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assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
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always @(negedge clk) begin
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if(RequestDelayedMIP) begin
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$display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]);
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@ -371,7 +414,8 @@ module testbench();
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fault = 0;
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if (`DEBUG_TRACE >= 1) begin
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`checkEQ("PCW",PCW,ExpectedPCW)
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`checkEQ("InstrW",InstrW,ExpectedInstrW)
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//`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
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// compressed to uncompressed conversion
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`checkEQ("Instr Count",dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW,InstrCountW)
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#2; // delay 2 ns.
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if(`DEBUG_TRACE >= 5) begin
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@ -397,19 +441,19 @@ module testbench();
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// check csr
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for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
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case(ExpectedCSRArrayW[NumCSRPostWIndex])
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"mhartid": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW)
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"mstatus": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW)
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"mtvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW)
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"mip": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIP_REGW)
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"mie": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIE_REGW)
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"mideleg":`CSRwarn(dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW)
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"medeleg": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW)
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"mepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MEPC_REGW)
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"mtval": `CSRwarn(dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW)
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"sepc": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.SEPC_REGW)
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"scause": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW)
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"stvec": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.STVEC_REGW)
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"stval": `CSRwarn(dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW)
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"mhartid": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW)
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"mstatus": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW)
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"mtvec": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW)
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"mip": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIP_REGW)
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"mie": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIE_REGW)
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"mideleg": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW)
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"medeleg": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW)
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"mepc": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MEPC_REGW)
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"mtval": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW)
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"sepc": `checkCSR(dut.hart.priv.csr.genblk1.csrs.SEPC_REGW)
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"scause": `checkCSR(dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW)
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"stvec": `checkCSR(dut.hart.priv.csr.genblk1.csrs.STVEC_REGW)
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"stval": `checkCSR(dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW)
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endcase
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end
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if (fault == 1) begin
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@ -429,63 +473,7 @@ module testbench();
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.ProgramLabelMapFile(ProgramLabelMapFile));
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///////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////// Testbench Core /////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// --------------
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// Initialization
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// --------------
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/*`ifdef CHECKPOINT
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var [`XLEN-1:0] initRF[31:1];
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var [`COUNTERS-1:3][`XLEN-1:0] initHPMCOUNTER;
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var [7:0][`PMP_ENTRIES-1:0] initPMPCFG;
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var [`XLEN-1:0][`PMP_ENTRIES-1:0] initPMPADDR;
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var initMIDELEG, initMCAUSE, initMCOUNTEREN, initMEDELEG, initMEPC, initMTVEC, initMIE,
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initMIP, initMSCRATCH, initMSTATUS, initSCAUSE, initSSCRATCH, initSATP, initSCOUNTEREN,
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initSEPC, initSTVEC;
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`endif*/
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`ifdef CHECKPOINT
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`define RF dut.hart.ieu.dp.regf.rf
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`define PC dut.hart.ifu.pcreg.q
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`define CSR_BASE dut.hart.priv.csr.genblk1
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`define HPMCOUNTER `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
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`define PMP_BASE `CSR_BASE.csrm.genblk4
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`define PMPCFG genblk2.PMPCFGreg.q
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`define PMPADDR PMPADDRreg.q
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`define MEDELEG `CSR_BASE.csrm.genblk1.MEDELEGreg.q
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`define MIDELEG `CSR_BASE.csrm.genblk1.MIDELEGreg.q
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`define MIE `CSR_BASE.csri.MIE_REGW
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`define MIP `CSR_BASE.csri.MIP_REGW
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`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
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`define SCAUSE `CSR_BASE.csrs.genblk1.SCAUSEreg.q
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`define MEPC `CSR_BASE.csrm.MEPCreg.q
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`define SEPC `CSR_BASE.csrs.genblk1.SEPCreg.q
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`define MCOUNTEREN `CSR_BASE.csrm.genblk3.MCOUNTERENreg.q
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`define SCOUNTEREN `CSR_BASE.csrs.genblk1.genblk3.SCOUNTERENreg.q
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`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
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`define SSCRATCH `CSR_BASE.csrs.genblk1.SSCRATCHreg.q
|
||||
`define MTVEC `CSR_BASE.csrm.MTVECreg.q
|
||||
`define STVEC `CSR_BASE.csrs.genblk1.STVECreg.q
|
||||
`define SATP `CSR_BASE.csrs.genblk1.genblk2.SATPreg.q
|
||||
`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
|
||||
`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
|
||||
`define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT
|
||||
`define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT
|
||||
`define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT
|
||||
`define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT
|
||||
`define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT
|
||||
`define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT
|
||||
`define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP
|
||||
`define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP
|
||||
`define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE
|
||||
`define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE
|
||||
`define STATUS_UPIE `CSR_BASE.csrsr.STATUS_UPIE
|
||||
`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
|
||||
`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
|
||||
`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
|
||||
`define CURR_PRIV dut.hart.priv.privmodereg.q
|
||||
`define INSTRET dut.hart.priv.csr.genblk1.counters.genblk1.genblk2.INSTRETreg.q
|
||||
|
||||
`define INIT_CHECKPOINT_VAL(SIGNAL_BASE,SIGNAL,DIM,LARGE_INDEX,SMALL_INDEX) \
|
||||
logic DIM init``SIGNAL [LARGE_INDEX:SMALL_INDEX]; \
|
||||
@ -573,36 +561,10 @@ module testbench();
|
||||
|
||||
|
||||
`endif
|
||||
initial begin
|
||||
reset <= 1; # 22; reset <= 0;
|
||||
$stop;
|
||||
end
|
||||
// initial loading of memories
|
||||
initial begin
|
||||
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
|
||||
`ifdef CHECKPOINT
|
||||
$readmemh({`CHECKPOINT_DIR,"ram.txt"}, dut.uncore.dtim.RAM);
|
||||
`else
|
||||
|
||||
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
|
||||
`endif
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||
ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
|
||||
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
|
||||
end
|
||||
|
||||
// -------
|
||||
// Running
|
||||
// -------
|
||||
always
|
||||
begin
|
||||
clk <= 1; # 5; clk <= 0; # 5;
|
||||
end
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////// Miscellaneous ///////////////////////////////
|
||||
//////////////////////////////// Extra Features ///////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Instr Opcode Tracking
|
||||
// For waveview convenience
|
||||
|
||||
Loading…
Reference in New Issue
Block a user