forked from Github_Repos/cvw
Major reorganization of regression and simulation and testbenches
This commit is contained in:
David Harris
parent
2b66615812
commit
75c17dc372
1024
wally-pipelined/config/rv32g/BTBPredictor.txt
Normal file
1024
wally-pipelined/config/rv32g/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
wally-pipelined/config/rv32g/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv32g/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
121
wally-pipelined/config/rv32g/wally-config.vh
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121
wally-pipelined/config/rv32g/wally-config.vh
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@ -0,0 +1,121 @@
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//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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||||
//
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||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// include shared configuration
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`include "wally-shared.vh"
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`define QEMU 0
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`define BUILDROOT 0
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`define BUSYBEAR 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 32
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`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define COUNTERS 32
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`define ZICOUNTERS_SUPPORTED 1
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 1
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`define MEM_DTIM 1
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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// TLB configuration. Entries should be a power of 2
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRIES 32
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
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`define DCACHE_NUMWAYS 4
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_BLOCKLENINBITS 256
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`define DCACHE_REPLBITS 3
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_BLOCKLENINBITS 256
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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// Address space
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`define RESET_VECTOR 32'h80000000
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIM_SUPPORTED 1'b1
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`define BOOTTIM_BASE 34'h00001000
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`define BOOTTIM_RANGE 34'h00000FFF
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`define TIM_SUPPORTED 1'b1
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`define TIM_BASE 34'h80000000
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`define TIM_RANGE 34'h07FFFFFF
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`define CLINT_SUPPORTED 1'b1
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`define CLINT_BASE 34'h02000000
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`define CLINT_RANGE 34'h0000FFFF
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`define GPIO_SUPPORTED 1'b1
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`define GPIO_BASE 34'h10012000
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`define GPIO_RANGE 34'h000000FF
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`define UART_SUPPORTED 1'b1
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`define UART_BASE 34'h10000000
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`define UART_RANGE 34'h00000007
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`define PLIC_SUPPORTED 1'b1
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`define PLIC_BASE 34'h0C000000
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`define PLIC_RANGE 34'h03FFFFFF
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// Bus Interface width
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`define AHBW 32
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 1
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 4
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -34,7 +34,7 @@
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 32
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`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0)
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`define MISA (32'h00000104)
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define COUNTERS 32
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@ -77,8 +77,6 @@
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
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`define BOOTTIM_SUPPORTED 1'b1
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`define BOOTTIM_BASE 34'h00001000
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`define BOOTTIM_RANGE 34'h00000FFF
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1024
wally-pipelined/config/rv64g/BTBPredictor.txt
Normal file
1024
wally-pipelined/config/rv64g/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
wally-pipelined/config/rv64g/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/rv64g/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
125
wally-pipelined/config/rv64g/wally-config.vh
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125
wally-pipelined/config/rv64g/wally-config.vh
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@ -0,0 +1,125 @@
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//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// include shared configuration
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`include "wally-shared.vh"
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`define QEMU 0
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`define BUILDROOT 0
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`define BUSYBEAR 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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// MISA RISC-V configuration per specification
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`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define COUNTERS 32
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`define ZICOUNTERS_SUPPORTED 1
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 1
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`define MEM_DTIM 1
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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// TLB configuration. Entries should be a power of 2
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRIES 32
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
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`define DCACHE_NUMWAYS 4
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_BLOCKLENINBITS 256
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`define DCACHE_REPLBITS 3
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_BLOCKLENINBITS 256
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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// Address space
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`define RESET_VECTOR 64'h0000000080000000
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// Bus Interface width
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`define AHBW 64
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// Peripheral Physiccal Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
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`define BOOTTIM_SUPPORTED 1'b1
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`define BOOTTIM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
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`define BOOTTIM_RANGE 56'h00000FFF
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`define TIM_SUPPORTED 1'b1
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`define TIM_BASE 56'h80000000
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`define TIM_RANGE 56'h7FFFFFFF
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`define CLINT_SUPPORTED 1'b1
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`define CLINT_BASE 56'h02000000
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`define CLINT_RANGE 56'h0000FFFF
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`define GPIO_SUPPORTED 1'b1
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`define GPIO_BASE 56'h10012000
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`define GPIO_RANGE 56'h000000FF
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`define UART_SUPPORTED 1'b1
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`define UART_BASE 56'h10000000
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`define UART_RANGE 56'h00000007
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`define PLIC_SUPPORTED 1'b1
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`define PLIC_BASE 56'h0C000000
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`define PLIC_RANGE 56'h03FFFFFF
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 1
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 4
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -35,7 +35,7 @@
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`define XLEN 64
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// MISA RISC-V configuration per specification
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`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define MISA (32'h00000104)
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define COUNTERS 32
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@ -67,7 +67,7 @@
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 1
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`define DIV_BITSPERCYCLE 4
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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24
wally-pipelined/regression/old/qrun.do
Normal file
24
wally-pipelined/regression/old/qrun.do
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@ -0,0 +1,24 @@
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# qrun.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Usage: do wally-pipelined-batch.do <config> <testcases>
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# Example: do wally-pipelined-batch.do rv32 imperas-32i
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# Use this wally-pipelined-batch.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined-batch.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined-batch.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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qrun -clean
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qrun +incdir+../config/rv32ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583 -optimize -snapshot wally +notimingchecks +nospecify
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qrun -simulate -snapshot wally
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qrun -simulate -snapshot wally
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215
wally-pipelined/regression/old/qrun.log
Normal file
215
wally-pipelined/regression/old/qrun.log
Normal file
@ -0,0 +1,215 @@
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QuestaSim-64 qrun 2021.2_1 Utility 2021.05 May 15 2021
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Start time: 21:17:08 on Oct 09,2021
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qrun -simulate -snapshot wally
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# vsim -lib qrun.out/work -c -do "run -all; quit -f" -statslog qrun.out/stats_log wally -appendlog -l qrun.log
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# Start time: 21:17:09 on Oct 09,2021
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# // Questa Sim-64
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# // Version 2021.2_1 linux_x86_64 May 15 2021
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# //
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# // Copyright 1991-2021 Mentor Graphics Corporation
|
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# // All Rights Reserved.
|
||||
# //
|
||||
# // QuestaSim and its associated documentation contain trade
|
||||
# // secrets and commercial or financial information that are the property of
|
||||
# // Mentor Graphics Corporation and are privileged, confidential,
|
||||
# // and exempt from disclosure under the Freedom of Information Act,
|
||||
# // 5 U.S.C. Section 552. Furthermore, this information
|
||||
# // is prohibited from disclosure under the Trade Secrets Act,
|
||||
# // 18 U.S.C. Section 1905.
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||||
# //
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# Loading sv_std.std
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||||
# Loading work.cla_sub52(fast)
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# Loading work.convert_inputs(fast)
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# Loading work.convert_inputs_div(fast)
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# Loading work.decoder(fast)
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# Loading work.faddcvt(fast)
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||||
# Loading work.floprc(fast)
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||||
# Loading work.fpudivsqrtrecur(fast)
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# Loading work.intdiv(fast)
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# Loading work.lz52(fast)
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# Loading work.qsel(fast)
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||||
# Loading work.ahbliteState(fast)
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# Loading work.testbench_sv_unit(fast)
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# Loading work.testbench(fast)
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# Loading work.regfile(fast)
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# Loading work.csrn(fast)
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# Loading work.instrTrackerTB(fast)
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# Loading work.instrNameDecTB(fast)
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# Loading work.copyShadow(fast)
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||||
# Loading work.tlbcamline(fast)
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# Loading work.pmpadrdec(fast)
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# Loading work.cacheway(fast)
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# Loading work.cacheway(fast__1)
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# run -all
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# ** Warning: Multiple Instruction Cache ways not yet implemented
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# Time: 0 ns Scope: testbench.riscvassertions File: ../testbench/testbench.sv Line: 327
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# ** Error: Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF
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# Time: 0 ns Scope: testbench.riscvassertions File: ../testbench/testbench.sv Line: 330
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# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ADD-01.elf.memfile
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# rv32i/I-ADD-01 succeeded. Brilliant!!!
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# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ADDI-01.elf.memfile
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# rv32i/I-ADDI-01 succeeded. Brilliant!!!
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||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-AND-01.elf.memfile
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# rv32i/I-AND-01 succeeded. Brilliant!!!
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# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ANDI-01.elf.memfile
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# rv32i/I-ANDI-01 succeeded. Brilliant!!!
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# Read memfile ../../imperas-riscv-tests/work/rv32i/I-AUIPC-01.elf.memfile
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# rv32i/I-AUIPC-01 succeeded. Brilliant!!!
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# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BEQ-01.elf.memfile
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# rv32i/I-BEQ-01 succeeded. Brilliant!!!
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||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BGE-01.elf.memfile
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# rv32i/I-BGE-01 succeeded. Brilliant!!!
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||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BGEU-01.elf.memfile
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||||
# rv32i/I-BGEU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BLT-01.elf.memfile
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||||
# rv32i/I-BLT-01 succeeded. Brilliant!!!
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||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BLTU-01.elf.memfile
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||||
# rv32i/I-BLTU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-BNE-01.elf.memfile
|
||||
# rv32i/I-BNE-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-DELAY_SLOTS-01.elf.memfile
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||||
# rv32i/I-DELAY_SLOTS-01 succeeded. Brilliant!!!
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||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-EBREAK-01.elf.memfile
|
||||
# rv32i/I-EBREAK-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ECALL-01.elf.memfile
|
||||
# rv32i/I-ECALL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ENDIANESS-01.elf.memfile
|
||||
# rv32i/I-ENDIANESS-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-IO-01.elf.memfile
|
||||
# rv32i/I-IO-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-JAL-01.elf.memfile
|
||||
# rv32i/I-JAL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-JALR-01.elf.memfile
|
||||
# rv32i/I-JALR-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LB-01.elf.memfile
|
||||
# 790020 Warning: access to memory address 0
|
||||
#
|
||||
# rv32i/I-LB-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LBU-01.elf.memfile
|
||||
# rv32i/I-LBU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LH-01.elf.memfile
|
||||
# rv32i/I-LH-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LHU-01.elf.memfile
|
||||
# rv32i/I-LHU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LUI-01.elf.memfile
|
||||
# rv32i/I-LUI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-LW-01.elf.memfile
|
||||
# rv32i/I-LW-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-MISALIGN_LDST-01.elf.memfile
|
||||
# rv32i/I-MISALIGN_LDST-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-NOP-01.elf.memfile
|
||||
# rv32i/I-NOP-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-OR-01.elf.memfile
|
||||
# rv32i/I-OR-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-ORI-01.elf.memfile
|
||||
# rv32i/I-ORI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-RF_size-01.elf.memfile
|
||||
# rv32i/I-RF_size-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-RF_width-01.elf.memfile
|
||||
# rv32i/I-RF_width-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-RF_x0-01.elf.memfile
|
||||
# rv32i/I-RF_x0-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SB-01.elf.memfile
|
||||
# 1233020 Warning: access to memory address 0
|
||||
#
|
||||
# rv32i/I-SB-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SH-01.elf.memfile
|
||||
# rv32i/I-SH-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLL-01.elf.memfile
|
||||
# rv32i/I-SLL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLLI-01.elf.memfile
|
||||
# rv32i/I-SLLI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLT-01.elf.memfile
|
||||
# rv32i/I-SLT-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLTI-01.elf.memfile
|
||||
# rv32i/I-SLTI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLTIU-01.elf.memfile
|
||||
# rv32i/I-SLTIU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SLTU-01.elf.memfile
|
||||
# rv32i/I-SLTU-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRA-01.elf.memfile
|
||||
# rv32i/I-SRA-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRAI-01.elf.memfile
|
||||
# rv32i/I-SRAI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRL-01.elf.memfile
|
||||
# rv32i/I-SRL-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SRLI-01.elf.memfile
|
||||
# rv32i/I-SRLI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SUB-01.elf.memfile
|
||||
# rv32i/I-SUB-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-SW-01.elf.memfile
|
||||
# rv32i/I-SW-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-XOR-01.elf.memfile
|
||||
# rv32i/I-XOR-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/I-XORI-01.elf.memfile
|
||||
# rv32i/I-XORI-01 succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ADD.elf.memfile
|
||||
# rv32i/WALLY-ADD succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SUB.elf.memfile
|
||||
# rv32i/WALLY-SUB succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ADDI.elf.memfile
|
||||
# rv32i/WALLY-ADDI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ANDI.elf.memfile
|
||||
# rv32i/WALLY-ANDI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-ORI.elf.memfile
|
||||
# rv32i/WALLY-ORI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-XORI.elf.memfile
|
||||
# rv32i/WALLY-XORI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SLTI.elf.memfile
|
||||
# rv32i/WALLY-SLTI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SLTIU.elf.memfile
|
||||
# rv32i/WALLY-SLTIU succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SLLI.elf.memfile
|
||||
# rv32i/WALLY-SLLI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SRLI.elf.memfile
|
||||
# rv32i/WALLY-SRLI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SRAI.elf.memfile
|
||||
# rv32i/WALLY-SRAI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-LOAD.elf.memfile
|
||||
# rv32i/WALLY-LOAD succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-SUB.elf.memfile
|
||||
# rv32i/WALLY-SUB succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-STORE.elf.memfile
|
||||
# rv32i/WALLY-STORE succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-JAL.elf.memfile
|
||||
# rv32i/WALLY-JAL succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-JALR.elf.memfile
|
||||
# rv32i/WALLY-JALR succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BEQ.elf.memfile
|
||||
# 2846200 Warning: access to memory address 0
|
||||
#
|
||||
# rv32i/WALLY-BEQ succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BNE.elf.memfile
|
||||
# rv32i/WALLY-BNE succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BLTU.elf.memfile
|
||||
# rv32i/WALLY-BLTU succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BLT.elf.memfile
|
||||
# rv32i/WALLY-BLT succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BGE.elf.memfile
|
||||
# rv32i/WALLY-BGE succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-BGEU.elf.memfile
|
||||
# rv32i/WALLY-BGEU succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRW.elf.memfile
|
||||
# rv32i/WALLY-CSRRW succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRS.elf.memfile
|
||||
# rv32i/WALLY-CSRRS succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRC.elf.memfile
|
||||
# rv32i/WALLY-CSRRC succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRWI.elf.memfile
|
||||
# rv32i/WALLY-CSRRWI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRSI.elf.memfile
|
||||
# rv32i/WALLY-CSRRSI succeeded. Brilliant!!!
|
||||
# Read memfile ../../imperas-riscv-tests/work/rv32i/WALLY-CSRRCI.elf.memfile
|
||||
# rv32i/WALLY-CSRRCI succeeded. Brilliant!!!
|
||||
# SUCCESS! All tests ran without failures.
|
||||
# ** Note: $stop : ../testbench/testbench.sv(244)
|
||||
# Time: 4170295 ns Iteration: 0 Instance: /testbench
|
||||
# Break at ../testbench/testbench.sv line 244
|
||||
# Stopped at ../testbench/testbench.sv line 244
|
||||
# quit -f
|
||||
# End time: 21:17:54 on Oct 09,2021, Elapsed time: 0:00:45
|
||||
# Errors: 1, Warnings: 1
|
||||
# *** Summary *********************************************
|
||||
# qrun: Errors: 0, Warnings: 0
|
||||
# vsim: Errors: 1, Warnings: 1
|
||||
# Totals: Errors: 1, Warnings: 1
|
||||
6
wally-pipelined/regression/old/qrun.out/history
Normal file
6
wally-pipelined/regression/old/qrun.out/history
Normal file
@ -0,0 +1,6 @@
|
||||
- Entry: 1
|
||||
Time: Sat Oct 9 21:16:56 2021
|
||||
Command: /cad/mentor/questa_sim-2021.2_1/questasim/linux_x86_64/qrun +incdir+../config/rv32ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/function_radix.sv ../testbench/common/instrNameDecTB.sv ../testbench/common/instrTrackerTB.sv ../testbench/common/logging.sv ../src/cache/cachereplacementpolicy.sv ../src/cache/cacheway.sv ../src/cache/dcache.sv ../src/cache/dcachefsm.sv ../src/cache/icache.sv ../src/cache/icachefsm.sv ../src/cache/sram1rw.sv ../src/ebu/ahblite.sv ../src/ebu/amoalu.sv ../src/fpu/adder.sv ../src/fpu/cla12.sv ../src/fpu/cla52.sv ../src/fpu/cla64.sv ../src/fpu/convert_inputs.sv ../src/fpu/convert_inputs_div.sv ../src/fpu/cvtfp.sv ../src/fpu/divconv.sv ../src/fpu/exception.sv ../src/fpu/exception_div.sv ../src/fpu/faddcvt.sv ../src/fpu/fclassify.sv ../src/fpu/fcmp.sv ../src/fpu/fctrl.sv ../src/fpu/fcvt.sv ../src/fpu/fhazard.sv ../src/fpu/fma.sv ../src/fpu/fpdiv.sv ../src/fpu/fpu.sv ../src/fpu/fpudivsqrtrecur.sv ../src/fpu/fpudivsqrtrecurcore.sv ../src/fpu/fregfile.sv ../src/fpu/fsgn.sv ../src/fpu/fsm.sv ../src/fpu/lzd_denorm.sv ../src/fpu/rounder_denorm.sv ../src/fpu/rounder_div.sv ../src/fpu/sbtm_a0.sv ../src/fpu/sbtm_a1.sv ../src/fpu/sbtm_a2.sv ../src/fpu/sbtm_a3.sv ../src/fpu/sbtm_div.sv ../src/fpu/sbtm_sqrt.sv ../src/fpu/shifter_denorm.sv ../src/fpu/unpacking.sv ../src/generic/adder.sv ../src/generic/clockgater.sv ../src/generic/flop.sv ../src/generic/lzd.sv ../src/generic/mux.sv ../src/generic/neg.sv ../src/generic/onehotdecoder.sv ../src/generic/or_rows.sv ../src/generic/shift.sv ../src/hazard/hazard.sv ../src/ieu/alu.sv ../src/ieu/controller.sv ../src/ieu/datapath.sv ../src/ieu/extend.sv ../src/ieu/forward.sv ../src/ieu/ieu.sv ../src/ieu/regfile.sv ../src/ieu/shifter.sv ../src/ifu/BTBPredictor.sv ../src/ifu/RAsPredictor.sv ../src/ifu/SRAM2P1R1W.sv ../src/ifu/bpred.sv ../src/ifu/decompress.sv ../src/ifu/globalHistoryPredictor.sv ../src/ifu/gsharePredictor.sv ../src/ifu/ifu.sv ../src/ifu/localHistoryPredictor.sv ../src/ifu/satCounter2.sv ../src/ifu/twoBitPredictor.sv ../src/lsu/lrsc.sv ../src/lsu/lsu.sv ../src/lsu/lsuArb.sv ../src/lsu/subwordread.sv ../src/mmu/adrdec.sv ../src/mmu/adrdecs.sv ../src/mmu/decoder.sv ../src/mmu/hptw.sv ../src/mmu/mmu.sv ../src/mmu/pmachecker.sv ../src/mmu/pmpadrdec.sv ../src/mmu/pmpchecker.sv ../src/mmu/priorityonehot.sv ../src/mmu/prioritythermometer.sv ../src/mmu/tlb.sv ../src/mmu/tlbcam.sv ../src/mmu/tlbcamline.sv ../src/mmu/tlbcontrol.sv ../src/mmu/tlblru.sv ../src/mmu/tlbmixer.sv ../src/mmu/tlbram.sv ../src/mmu/tlbramline.sv ../src/muldiv/div.sv ../src/muldiv/intdivrestoring.sv ../src/muldiv/intdivrestoringstep.sv ../src/muldiv/mul.sv ../src/muldiv/muldiv.sv ../src/privileged/csr.sv ../src/privileged/csrc.sv ../src/privileged/csri.sv ../src/privileged/csrm.sv ../src/privileged/csrn.sv ../src/privileged/csrs.sv ../src/privileged/csrsr.sv ../src/privileged/csru.sv ../src/privileged/privdec.sv ../src/privileged/privileged.sv ../src/privileged/trap.sv ../src/uncore/clint.sv ../src/uncore/dtim.sv ../src/uncore/gpio.sv ../src/uncore/plic.sv ../src/uncore/subwordwrite.sv ../src/uncore/uart.sv ../src/uncore/uartPC16550D.sv ../src/uncore/uncore.sv ../src/wally/wallypipelinedhart.sv ../src/wally/wallypipelinedsoc.sv -suppress 2583 -optimize -snapshot wally +notimingchecks +nospecify
|
||||
- Entry: 2
|
||||
Time: Sat Oct 9 21:17:08 2021
|
||||
Command: /cad/mentor/questa_sim-2021.2_1/questasim/linux_x86_64/qrun -simulate -snapshot wally
|
||||
1
wally-pipelined/regression/old/qrun.out/history.cnt
Normal file
1
wally-pipelined/regression/old/qrun.out/history.cnt
Normal file
@ -0,0 +1 @@
|
||||
2
|
||||
BIN
wally-pipelined/regression/old/qrun.out/sessions/qrun.out$work
Normal file
BIN
wally-pipelined/regression/old/qrun.out/sessions/qrun.out$work
Normal file
Binary file not shown.
2
wally-pipelined/regression/old/qrun.out/stats_log
Normal file
2
wally-pipelined/regression/old/qrun.out/stats_log
Normal file
@ -0,0 +1,2 @@
|
||||
qrun: Errors: 0, Warnings: 0
|
||||
vsim: Errors: 1, Warnings: 1
|
||||
1
wally-pipelined/regression/old/qrun.out/top_dus
Normal file
1
wally-pipelined/regression/old/qrun.out/top_dus
Normal file
@ -0,0 +1 @@
|
||||
/mnt/scratch/harris_scratch/riscv-wally/wally-pipelined/regression/qrun.out/work 0 compiled
|
||||
1
wally-pipelined/regression/old/qrun.out/version
Normal file
1
wally-pipelined/regression/old/qrun.out/version
Normal file
@ -0,0 +1 @@
|
||||
qrun 0.5
|
||||
1
wally-pipelined/regression/old/sim-buildroot
Executable file
1
wally-pipelined/regression/old/sim-buildroot
Executable file
@ -0,0 +1 @@
|
||||
vsim -do wally-buildroot.do
|
||||
3
wally-pipelined/regression/old/sim-buildroot-batch
Executable file
3
wally-pipelined/regression/old/sim-buildroot-batch
Executable file
@ -0,0 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-buildroot-batch.do
|
||||
!
|
||||
3
wally-pipelined/regression/old/sim-wally-batch-rv32ic
Executable file
3
wally-pipelined/regression/old/sim-wally-batch-rv32ic
Executable file
@ -0,0 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-pipelined-batch.do rv32ic imperas-32i
|
||||
!
|
||||
@ -33,26 +33,6 @@ configs = [
|
||||
cmd="vsim -do wally-buildroot-batch.do -c > {}",
|
||||
grepstr="8500000 instructions"
|
||||
),
|
||||
TestCase(
|
||||
name="arch64",
|
||||
cmd="vsim > {} -c <<!\ndo wally-arch.do ../config/rv64ic rv64ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
),
|
||||
TestCase(
|
||||
name="arch32",
|
||||
cmd="vsim > {} -c <<!\ndo wally-arch.do ../config/rv32ic rv32ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
),
|
||||
TestCase(
|
||||
name="rv32ic",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do ../config/rv32ic rv32ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
),
|
||||
TestCase(
|
||||
name="rv64ic",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do ../config/rv64ic rv64ic\n!",
|
||||
grepstr="All tests ran without failures"
|
||||
),
|
||||
TestCase(
|
||||
name="lints",
|
||||
cmd="../lint-wally &> {}",
|
||||
@ -60,6 +40,23 @@ configs = [
|
||||
),
|
||||
]
|
||||
|
||||
tests64 = ["arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"]
|
||||
for test in tests64:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
|
||||
for test in tests32:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32g "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
|
||||
import os
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
||||
@ -70,7 +67,7 @@ def search_log_for_text(text, logfile):
|
||||
|
||||
def run_test_case(config):
|
||||
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
|
||||
logname = "regression_logs/wally_"+config.name+".log"
|
||||
logname = "logs/wally_"+config.name+".log"
|
||||
cmd = config.cmd.format(logname)
|
||||
print(cmd)
|
||||
os.system(cmd)
|
||||
@ -85,13 +82,13 @@ def run_test_case(config):
|
||||
def main():
|
||||
"""Run the tests and count the failures"""
|
||||
# Scale the number of concurrent processes to the number of test cases, but
|
||||
# max out at 12 concurrent processes to not overwhelm the system
|
||||
# max out at a limited number of concurrent processes to not overwhelm the system
|
||||
TIMEOUT_DUR = 1800 # seconds
|
||||
try:
|
||||
os.mkdir("regression_logs")
|
||||
os.mkdir("logs")
|
||||
except:
|
||||
pass
|
||||
with Pool(processes=min(len(configs),12)) as pool:
|
||||
with Pool(processes=min(len(configs),25)) as pool:
|
||||
num_fail = 0
|
||||
results = {}
|
||||
for config in configs:
|
||||
|
||||
@ -1,3 +0,0 @@
|
||||
#!/bin/sh
|
||||
vsim -do $1
|
||||
|
||||
@ -1 +1,2 @@
|
||||
vsim -do wally-pipelined.do
|
||||
vsim -do "do wally-pipelined.do rv32g arch32m"
|
||||
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-pipelined-batch.do ../config/rv64ic rv64ic
|
||||
do wally-pipelined-batch.do rv64g arch64m
|
||||
!
|
||||
|
||||
@ -1,3 +0,0 @@
|
||||
vsim -c <<!
|
||||
do wally-pipelined-batch.do ../config/rv32ic rv32ic
|
||||
!
|
||||
@ -1,22 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
int main() {
|
||||
|
||||
uint64_t N;
|
||||
uint64_t D;
|
||||
uint64_t Q;
|
||||
|
||||
D = 0xdf7f3844121bcc23;
|
||||
N = 0x10fd3dedadea5195;
|
||||
Q = N/D;
|
||||
|
||||
printf("N = %" PRIx64 "\n", N);
|
||||
printf("D = %" PRIx64 "\n", D);
|
||||
printf("Q = %" PRIx64 "\n", Q);
|
||||
printf("R = %" PRIx64 "\n", N%D);
|
||||
|
||||
|
||||
|
||||
}
|
||||
@ -7,6 +7,9 @@
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-pipelined-batch.do <config> <testcases>
|
||||
# Example: do wally-pipelined-batch.do rv32ic imperas-32i
|
||||
|
||||
# Use this wally-pipelined-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined-batch.do
|
||||
@ -17,10 +20,10 @@
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work_$2] {
|
||||
vdel -lib work_$2 -all
|
||||
if [file exists work_${1}_${2}] {
|
||||
vdel -lib work_${1}_${2} -all
|
||||
}
|
||||
vlib work_$2
|
||||
vlib work_${1}_${2}
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
@ -29,15 +32,12 @@ vlib work_$2
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
|
||||
switch $argc {
|
||||
0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
}
|
||||
vlog -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt work_$2.testbench -work work_$2 -o workopt_$2
|
||||
vsim -lib work_$2 workopt_$2
|
||||
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt
|
||||
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
|
||||
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
|
||||
#vsim -coverage -lib work_$2 workopt_$2
|
||||
|
||||
@ -7,6 +7,8 @@
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
@ -29,13 +31,14 @@ vlib work
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
switch $argc {
|
||||
0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
}
|
||||
#switch $argc {
|
||||
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
#}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt +acc work.testbench -o workopt
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
|
||||
vopt +acc work.testbench -G TEST=$2 -o workopt
|
||||
vsim workopt
|
||||
|
||||
view wave
|
||||
@ -46,5 +49,6 @@ do ./wave-dos/peripheral-waves.do
|
||||
#run 3600
|
||||
run -all
|
||||
#quit
|
||||
noview ../testbench/testbench-imperas.sv
|
||||
#noview ../testbench/testbench-imperas.sv
|
||||
noview ../testbench/testbench.sv
|
||||
view wave
|
||||
|
||||
38
wally-pipelined/src/generic/counter.sv
Normal file
38
wally-pipelined/src/generic/counter.sv
Normal file
@ -0,0 +1,38 @@
|
||||
///////////////////////////////////////////
|
||||
// counter.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 10 October 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Counter with reset and enable
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module counter #(parameter WIDTH=8) (
|
||||
input logic clk, reset, en,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
logic [WIDTH-1:0] qnext;
|
||||
|
||||
assign qnext = q + 1;
|
||||
flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
|
||||
endmodule
|
||||
|
||||
|
||||
@ -54,6 +54,9 @@ module mul (
|
||||
|
||||
// portions of product
|
||||
assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]};
|
||||
|
||||
// *** assumes unsigned multiplication
|
||||
// DW02_multp #((`XLEN-1), (`XLEN-1), 2*(`XLEN-1)) multp_dw( .a(SrcAE[`XLEN-2:0]), .b(SrcBE[`XLEN-2:0]), .tc(1'b0), .out0(Pprime0), .out1(Pprime1) );
|
||||
assign PA = {(`XLEN-1){SrcAE[`XLEN-1]}} & SrcBE[`XLEN-2:0];
|
||||
assign PB = {(`XLEN-1){SrcBE[`XLEN-1]}} & SrcAE[`XLEN-2:0];
|
||||
assign PP = SrcAE[`XLEN-1] & SrcBE[`XLEN-1];
|
||||
@ -72,6 +75,8 @@ module mul (
|
||||
else if (MULHSU) PP4 = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}};
|
||||
else PP4 = {1'b0, PP, {(`XLEN*2-2){1'b0}}};
|
||||
|
||||
// ***Put register before this final addition
|
||||
assign ProdE = PP1 + PP2 + PP3 + PP4; //SrcAE * SrcBE;
|
||||
// assign ProdE = Pprime0 + Pprime1 + PP2 + PP3 + PP4; //SrcAE * SrcBE;
|
||||
endmodule
|
||||
|
||||
|
||||
Binary file not shown.
@ -1,780 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// testbench-imperas.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Wally Testbench and helper modules
|
||||
// Applies test programs from the Imperas suite
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module testbench();
|
||||
parameter DEBUG = 0;
|
||||
parameter TESTSPERIPH = 0; // set to 0 for regression
|
||||
parameter TESTSPRIV = 0; // set to 0 for regression
|
||||
|
||||
logic clk;
|
||||
logic reset;
|
||||
|
||||
parameter SIGNATURESIZE = 5000000;
|
||||
|
||||
int test, i, errors, totalerrors;
|
||||
logic [31:0] sig32[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] testadr;
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
logic [`XLEN-1:0] meminit;
|
||||
|
||||
string tests32mmu[] = '{
|
||||
"rv32mmu/WALLY-MMU-SV32", "3000"
|
||||
//"rv32mmu/WALLY-PMA", "3000",
|
||||
//"rv32mmu/WALLY-PMA", "3000"
|
||||
};
|
||||
|
||||
string tests64mmu[] = '{
|
||||
"rv64mmu/WALLY-MMU-SV48", "3000",
|
||||
"rv64mmu/WALLY-MMU-SV39", "3000"
|
||||
//"rv64mmu/WALLY-PMA", "3000",
|
||||
//"rv64mmu/WALLY-PMA", "3000"
|
||||
};
|
||||
|
||||
|
||||
string tests32f[] = '{
|
||||
"rv32f/I-FADD-S-01", "2000",
|
||||
"rv32f/I-FCLASS-S-01", "2000",
|
||||
"rv32f/I-FCVT-S-W-01", "2000",
|
||||
"rv32f/I-FCVT-S-WU-01", "2000",
|
||||
"rv32f/I-FCVT-W-S-01", "2000",
|
||||
"rv32f/I-FCVT-WU-S-01", "2000",
|
||||
"rv32f/I-FDIV-S-01", "2000",
|
||||
"rv32f/I-FEQ-S-01", "2000",
|
||||
"rv32f/I-FLE-S-01", "2000",
|
||||
"rv32f/I-FLT-S-01", "2000",
|
||||
"rv32f/I-FMADD-S-01", "2000",
|
||||
"rv32f/I-FMAX-S-01", "2000",
|
||||
"rv32f/I-FMIN-S-01", "2000",
|
||||
"rv32f/I-FMSUB-S-01", "2000",
|
||||
"rv32f/I-FMUL-S-01", "2000",
|
||||
"rv32f/I-FMV-W-X-01", "2000",
|
||||
"rv32f/I-FMV-X-W-01", "2000",
|
||||
"rv32f/I-FNMADD-S-01", "2000",
|
||||
"rv32f/I-FNMSUB-S-01", "2000",
|
||||
"rv32f/I-FSGNJ-S-01", "2000",
|
||||
"rv32f/I-FSGNJN-S-01", "2000",
|
||||
"rv32f/I-FSGNJX-S-01", "2000",
|
||||
"rv32f/I-FSQRT-S-01", "2000",
|
||||
"rv32f/I-FSW-01", "2000",
|
||||
"rv32f/I-FLW-01", "2110",
|
||||
"rv32f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
string tests64f[] = '{
|
||||
"rv64f/I-FLW-01", "2110",
|
||||
"rv64f/I-FMV-W-X-01", "2000",
|
||||
"rv64f/I-FMV-X-W-01", "2000",
|
||||
"rv64f/I-FSW-01", "2000",
|
||||
"rv64f/I-FCLASS-S-01", "2000",
|
||||
"rv64f/I-FADD-S-01", "2000",
|
||||
// "rv64f/I-FCVT-S-L-01", "2000",
|
||||
// "rv64f/I-FCVT-S-LU-01", "2000",
|
||||
// "rv64f/I-FCVT-S-W-01", "2000",
|
||||
// "rv64f/I-FCVT-S-WU-01", "2000",
|
||||
"rv64f/I-FCVT-L-S-01", "2000",
|
||||
"rv64f/I-FCVT-LU-S-01", "2000",
|
||||
"rv64f/I-FCVT-W-S-01", "2000",
|
||||
"rv64f/I-FCVT-WU-S-01", "2000",
|
||||
"rv64f/I-FDIV-S-01", "2000",
|
||||
"rv64f/I-FEQ-S-01", "2000",
|
||||
"rv64f/I-FLE-S-01", "2000",
|
||||
"rv64f/I-FLT-S-01", "2000",
|
||||
"rv64f/I-FMADD-S-01", "2000",
|
||||
"rv64f/I-FMAX-S-01", "2000",
|
||||
"rv64f/I-FMIN-S-01", "2000",
|
||||
"rv64f/I-FMSUB-S-01", "2000",
|
||||
"rv64f/I-FMUL-S-01", "2000",
|
||||
"rv64f/I-FNMADD-S-01", "2000",
|
||||
"rv64f/I-FNMSUB-S-01", "2000",
|
||||
"rv64f/I-FSGNJ-S-01", "2000",
|
||||
"rv64f/I-FSGNJN-S-01", "2000",
|
||||
"rv64f/I-FSGNJX-S-01", "2000",
|
||||
"rv64f/I-FSQRT-S-01", "2000",
|
||||
"rv64f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
string tests64d[] = '{
|
||||
"rv64d/I-FSD-01", "2000",
|
||||
"rv64d/I-FLD-01", "2420",
|
||||
"rv64d/I-FMV-X-D-01", "2000",
|
||||
"rv64d/I-FMV-D-X-01", "2000",
|
||||
"rv64d/I-FDIV-D-01", "2000",
|
||||
"rv64d/I-FNMADD-D-01", "2000",
|
||||
"rv64d/I-FNMSUB-D-01", "2000",
|
||||
"rv64d/I-FMSUB-D-01", "2000",
|
||||
"rv64d/I-FMAX-D-01", "2000",
|
||||
"rv64d/I-FMIN-D-01", "2000",
|
||||
"rv64d/I-FLE-D-01", "2000",
|
||||
"rv64d/I-FLT-D-01", "2000",
|
||||
"rv64d/I-FEQ-D-01", "2000",
|
||||
"rv64d/I-FADD-D-01", "2000",
|
||||
"rv64d/I-FCLASS-D-01", "2000",
|
||||
"rv64d/I-FMADD-D-01", "2000",
|
||||
"rv64d/I-FMUL-D-01", "2000",
|
||||
"rv64d/I-FSGNJ-D-01", "2000",
|
||||
"rv64d/I-FSGNJN-D-01", "2000",
|
||||
"rv64d/I-FSGNJX-D-01", "2000",
|
||||
"rv64d/I-FSQRT-D-01", "2000",
|
||||
"rv64d/I-FSUB-D-01", "2000",
|
||||
// "rv64d/I-FCVT-D-L-01", "2000",
|
||||
// "rv64d/I-FCVT-D-LU-01", "2000",
|
||||
"rv64d/I-FCVT-D-S-01", "2000",
|
||||
// "rv64d/I-FCVT-D-W-01", "2000",
|
||||
// "rv64d/I-FCVT-D-WU-01", "2000",
|
||||
"rv64d/I-FCVT-L-D-01", "2000",
|
||||
"rv64d/I-FCVT-LU-D-01", "2000",
|
||||
"rv64d/I-FCVT-S-D-01", "2000",
|
||||
"rv64d/I-FCVT-W-D-01", "2000",
|
||||
"rv64d/I-FCVT-WU-D-01", "2000"
|
||||
};
|
||||
|
||||
string tests64a[] = '{
|
||||
"rv64a/WALLY-AMO", "2110",
|
||||
"rv64a/WALLY-LRSC", "2110"
|
||||
};
|
||||
|
||||
string tests64priv[] = '{
|
||||
"rv64i_m/privilege/ebreak", "2090",
|
||||
"rv64i_m/privilege/ecall", "2090",
|
||||
"rv64i_m/privilege/misalign-beq-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bge-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bgeu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-blt-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bltu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bne-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-jal-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-ld-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lh-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lhu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lw-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lwu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-sd-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-sh-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-sw-01", "20a0",
|
||||
"rv64i_m/privilege/misalign1-jalr-01", "20a0",
|
||||
"rv64i_m/privilege/misalign2-jalr-01", "20a0"
|
||||
};
|
||||
|
||||
string tests64m[] = '{
|
||||
"rv64i_m/M/div-01", "9010",
|
||||
"rv64i_m/M/divu-01", "a010",
|
||||
"rv64i_m/M/divuw-01", "a010",
|
||||
"rv64i_m/M/divw-01", "9010",
|
||||
"rv64i_m/M/mul-01", "9010",
|
||||
"rv64i_m/M/mulh-01", "9010",
|
||||
"rv64i_m/M/mulhsu-01", "9010",
|
||||
"rv64i_m/M/mulhu-01", "a010",
|
||||
"rv64i_m/M/mulw-01", "9010",
|
||||
"rv64i_m/M/rem-01", "9010",
|
||||
"rv64i_m/M/remu-01", "a010",
|
||||
"rv64i_m/M/remuw-01", "a010",
|
||||
"rv64i_m/M/remw-01", "9010"
|
||||
};
|
||||
|
||||
string tests64ic[] = '{
|
||||
"rv64i_m/C/cadd-01", "8010",
|
||||
"rv64i_m/C/caddi-01", "4010",
|
||||
"rv64i_m/C/caddi16sp-01", "2010",
|
||||
"rv64i_m/C/caddi4spn-01", "2010",
|
||||
"rv64i_m/C/caddiw-01", "4010",
|
||||
"rv64i_m/C/caddw-01", "8010",
|
||||
"rv64i_m/C/cand-01", "8010",
|
||||
"rv64i_m/C/candi-01", "4010",
|
||||
"rv64i_m/C/cbeqz-01", "4010",
|
||||
"rv64i_m/C/cbnez-01", "5010",
|
||||
"rv64i_m/C/cebreak-01", "2070",
|
||||
"rv64i_m/C/cj-01", "3010",
|
||||
"rv64i_m/C/cjalr-01", "2010",
|
||||
"rv64i_m/C/cjr-01", "2010",
|
||||
"rv64i_m/C/cld-01", "2010",
|
||||
"rv64i_m/C/cldsp-01", "2010",
|
||||
"rv64i_m/C/cli-01", "2010",
|
||||
"rv64i_m/C/clui-01", "2010",
|
||||
"rv64i_m/C/clw-01", "2010",
|
||||
"rv64i_m/C/clwsp-01", "2010",
|
||||
"rv64i_m/C/cmv-01", "2010",
|
||||
"rv64i_m/C/cnop-01", "2010",
|
||||
"rv64i_m/C/cor-01", "8010",
|
||||
"rv64i_m/C/csd-01", "3010",
|
||||
"rv64i_m/C/csdsp-01", "3010",
|
||||
"rv64i_m/C/cslli-01", "2010",
|
||||
"rv64i_m/C/csrai-01", "2010",
|
||||
"rv64i_m/C/csrli-01", "2010",
|
||||
"rv64i_m/C/csub-01", "8010",
|
||||
"rv64i_m/C/csubw-01", "8010",
|
||||
"rv64i_m/C/csw-01", "3010",
|
||||
"rv64i_m/C/cswsp-01", "3010",
|
||||
"rv64i_m/C/cxor-01", "8010"
|
||||
};
|
||||
|
||||
string tests64i[] = '{
|
||||
"rv64i_m/I/add-01", "9010",
|
||||
"rv64i_m/I/addi-01", "6010",
|
||||
"rv64i_m/I/addiw-01", "6010",
|
||||
"rv64i_m/I/addw-01", "9010",
|
||||
"rv64i_m/I/and-01", "9010",
|
||||
"rv64i_m/I/andi-01", "6010",
|
||||
"rv64i_m/I/auipc-01", "2010",
|
||||
"rv64i_m/I/beq-01", "47010",
|
||||
"rv64i_m/I/bge-01", "47010",
|
||||
"rv64i_m/I/bgeu-01", "56010",
|
||||
"rv64i_m/I/blt-01", "4d010",
|
||||
"rv64i_m/I/bltu-01", "57010",
|
||||
"rv64i_m/I/bne-01", "43010",
|
||||
"rv64i_m/I/fence-01", "2010",
|
||||
"rv64i_m/I/jal-01", "122010",
|
||||
"rv64i_m/I/jalr-01", "2010",
|
||||
"rv64i_m/I/lb-align-01", "2010",
|
||||
"rv64i_m/I/lbu-align-01", "2010",
|
||||
"rv64i_m/I/ld-align-01", "2010",
|
||||
"rv64i_m/I/lh-align-01", "2010",
|
||||
"rv64i_m/I/lhu-align-01", "2010",
|
||||
"rv64i_m/I/lui-01", "2010",
|
||||
"rv64i_m/I/lw-align-01", "2010",
|
||||
"rv64i_m/I/lwu-align-01", "2010",
|
||||
"rv64i_m/I/or-01", "9010",
|
||||
"rv64i_m/I/ori-01", "6010",
|
||||
"rv64i_m/I/sb-align-01", "3010",
|
||||
"rv64i_m/I/sd-align-01", "3010",
|
||||
"rv64i_m/I/sh-align-01", "3010",
|
||||
"rv64i_m/I/sll-01", "3010",
|
||||
"rv64i_m/I/slli-01", "2010",
|
||||
"rv64i_m/I/slliw-01", "2010",
|
||||
"rv64i_m/I/sllw-01", "3010",
|
||||
"rv64i_m/I/slt-01", "9010",
|
||||
"rv64i_m/I/slti-01", "6010",
|
||||
"rv64i_m/I/sltiu-01", "6010",
|
||||
"rv64i_m/I/sltu-01", "a010",
|
||||
"rv64i_m/I/sra-01", "3010",
|
||||
"rv64i_m/I/srai-01", "2010",
|
||||
"rv64i_m/I/sraiw-01", "2010",
|
||||
"rv64i_m/I/sraw-01", "3010",
|
||||
"rv64i_m/I/srl-01", "3010",
|
||||
"rv64i_m/I/srli-01", "2010",
|
||||
"rv64i_m/I/srliw-01", "2010",
|
||||
"rv64i_m/I/srlw-01", "3010",
|
||||
"rv64i_m/I/sub-01", "9010",
|
||||
"rv64i_m/I/subw-01", "9010",
|
||||
"rv64i_m/I/sw-align-01", "3010",
|
||||
"rv64i_m/I/xor-01", "9010",
|
||||
"rv64i_m/I/xori-01", "6010"
|
||||
};
|
||||
|
||||
string tests32priv[] = '{
|
||||
"rv32i_m/privilege/ebreak", "2070",
|
||||
"rv32i_m/privilege/ecall", "2070",
|
||||
"rv32i_m/privilege/misalign-beq-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bge-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bgeu-01", "2080",
|
||||
"rv32i_m/privilege/misalign-blt-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bltu-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bne-01", "2080",
|
||||
"rv32i_m/privilege/misalign-jal-01", "2080",
|
||||
"rv32i_m/privilege/misalign-lh-01", "2080",
|
||||
"rv32i_m/privilege/misalign-lhu-01", "2080",
|
||||
"rv32i_m/privilege/misalign-lw-01", "2080",
|
||||
"rv32i_m/privilege/misalign-sh-01", "2080",
|
||||
"rv32i_m/privilege/misalign-sw-01", "2080",
|
||||
"rv32i_m/privilege/misalign1-jalr-01", "2080",
|
||||
"rv32i_m/privilege/misalign2-jalr-01", "2080"
|
||||
};
|
||||
|
||||
string tests32m[] = '{
|
||||
"rv32i_m/M/div-01", "5010",
|
||||
"rv32i_m/M/divu-01", "5010",
|
||||
"rv32i_m/M/mul-01", "5010",
|
||||
"rv32i_m/M/mulh-01", "5010",
|
||||
"rv32i_m/M/mulhsu-01", "5010",
|
||||
"rv32i_m/M/mulhu-01", "5010",
|
||||
"rv32i_m/M/rem-01", "5010",
|
||||
"rv32i_m/M/remu-01", "5010"
|
||||
};
|
||||
|
||||
string tests32ic[] = '{
|
||||
"rv32i_m/C/cadd-01", "4010",
|
||||
"rv32i_m/C/caddi-01", "3010",
|
||||
"rv32i_m/C/caddi16sp-01", "2010",
|
||||
"rv32i_m/C/caddi4spn-01", "2010",
|
||||
"rv32i_m/C/cand-01", "4010",
|
||||
"rv32i_m/C/candi-01", "3010",
|
||||
"rv32i_m/C/cbeqz-01", "3010",
|
||||
"rv32i_m/C/cbnez-01", "3010",
|
||||
"rv32i_m/C/cebreak-01", "2050",
|
||||
"rv32i_m/C/cj-01", "3010",
|
||||
"rv32i_m/C/cjal-01", "3010",
|
||||
"rv32i_m/C/cjalr-01", "2010",
|
||||
"rv32i_m/C/cjr-01", "2010",
|
||||
"rv32i_m/C/cli-01", "2010",
|
||||
"rv32i_m/C/clui-01", "2010",
|
||||
"rv32i_m/C/clw-01", "2010",
|
||||
"rv32i_m/C/clwsp-01", "2010",
|
||||
"rv32i_m/C/cmv-01", "2010",
|
||||
"rv32i_m/C/cnop-01", "2010",
|
||||
"rv32i_m/C/cor-01", "4010",
|
||||
"rv32i_m/C/cslli-01", "2010",
|
||||
"rv32i_m/C/csrai-01", "2010",
|
||||
"rv32i_m/C/csrli-01", "2010",
|
||||
"rv32i_m/C/csub-01", "4010",
|
||||
"rv32i_m/C/csw-01", "2010",
|
||||
"rv32i_m/C/cswsp-01", "2010",
|
||||
"rv32i_m/C/cxor-01", "4010"
|
||||
};
|
||||
|
||||
string tests32i[] = '{
|
||||
"rv32i_m/I/add-01", "5010",
|
||||
"rv32i_m/I/addi-01", "4010",
|
||||
"rv32i_m/I/and-01", "5010",
|
||||
"rv32i_m/I/andi-01", "4010",
|
||||
"rv32i_m/I/auipc-01", "2010",
|
||||
"rv32i_m/I/beq-01", "39010",
|
||||
"rv32i_m/I/bge-01", "3a010",
|
||||
"rv32i_m/I/bgeu-01", "4a010",
|
||||
"rv32i_m/I/blt-01", "38010",
|
||||
"rv32i_m/I/bltu-01", "4b010",
|
||||
"rv32i_m/I/bne-01", "39010",
|
||||
"rv32i_m/I/fence-01", "2010",
|
||||
"rv32i_m/I/jal-01", "1ad010",
|
||||
"rv32i_m/I/jalr-01", "2010",
|
||||
"rv32i_m/I/lb-align-01", "2010",
|
||||
"rv32i_m/I/lbu-align-01", "2010",
|
||||
"rv32i_m/I/lh-align-01", "2010",
|
||||
"rv32i_m/I/lhu-align-01", "2010",
|
||||
"rv32i_m/I/lui-01", "2010",
|
||||
"rv32i_m/I/lw-align-01", "2010",
|
||||
"rv32i_m/I/or-01", "5010",
|
||||
"rv32i_m/I/ori-01", "4010",
|
||||
"rv32i_m/I/sb-align-01", "2010",
|
||||
"rv32i_m/I/sh-align-01", "2010",
|
||||
"rv32i_m/I/sll-01", "2010",
|
||||
"rv32i_m/I/slli-01", "2010",
|
||||
"rv32i_m/I/slt-01", "5010",
|
||||
"rv32i_m/I/slti-01", "4010",
|
||||
"rv32i_m/I/sltiu-01", "4010",
|
||||
"rv32i_m/I/sltu-01", "5010",
|
||||
"rv32i_m/I/sra-01", "2010",
|
||||
"rv32i_m/I/srai-01", "2010",
|
||||
"rv32i_m/I/srl-01", "2010",
|
||||
"rv32i_m/I/srli-01", "2010",
|
||||
"rv32i_m/I/sub-01", "5010",
|
||||
"rv32i_m/I/sw-align-01", "2010",
|
||||
"rv32i_m/I/xor-01", "5010",
|
||||
"rv32i_m/I/xori-01", "4010"
|
||||
};
|
||||
|
||||
string tests[];
|
||||
string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||
logic [`AHBW-1:0] HRDATAEXT;
|
||||
logic HREADYEXT, HRESPEXT;
|
||||
logic [31:0] HADDR;
|
||||
logic [`AHBW-1:0] HWDATA;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
logic [3:0] HPROT;
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic HCLK, HRESETn;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic DCacheFlushDone, DCacheFlushStart;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
|
||||
// check assertions for a legal configuration
|
||||
riscvassertions riscvassertions();
|
||||
logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
if (`XLEN == 64) begin // RV64
|
||||
if (`TESTSBP) begin
|
||||
//tests = testsBP64;
|
||||
// testsbp should not run the other tests. It starts at address 0 rather than
|
||||
// 0x8000_0000, the next if must remain an else if.
|
||||
end else if (TESTSPERIPH)
|
||||
//tests = tests64periph;
|
||||
tests = {};
|
||||
else if (TESTSPRIV)
|
||||
//tests = tests64p;
|
||||
tests = {};
|
||||
else begin
|
||||
tests = {tests64priv, tests64i};
|
||||
// tests = {tests64p,tests64i, tests64periph};
|
||||
if (`C_SUPPORTED) tests = {tests, tests64ic};
|
||||
// else tests = {tests, tests64iNOc};
|
||||
if (`M_SUPPORTED) tests = {tests64m, tests};
|
||||
/* if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||
if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
|
||||
if (`A_SUPPORTED) tests = {tests64a, tests}; */
|
||||
end
|
||||
//tests = {tests64a, tests};
|
||||
end else begin // RV32
|
||||
// *** add the 32 bit bp tests
|
||||
if (TESTSPERIPH)
|
||||
//tests = tests32periph;
|
||||
tests = {};
|
||||
else if (TESTSPRIV)
|
||||
//tests = tests32p;
|
||||
tests = {};
|
||||
else begin
|
||||
tests = {tests32priv, tests32i};
|
||||
//tests = {tests32i, tests32priv};
|
||||
if (`C_SUPPORTED) tests = {tests, tests32ic};
|
||||
if (`M_SUPPORTED) tests = {tests32m, tests};
|
||||
//if (`C_SUPPORTED) tests = {tests32ic, tests};
|
||||
//if (`M_SUPPORTED) tests = {tests32m, tests};
|
||||
/* tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment
|
||||
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
|
||||
else tests = {tests, tests32iNOc};
|
||||
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
|
||||
if (`F_SUPPORTED) tests = {tests32f, tests};
|
||||
if (`MEM_VIRTMEM) tests = {tests32mmu, tests};
|
||||
if (`A_SUPPORTED) tests = {tests32a, tests}; */
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
string tvroot, bootroot, signame, memfilename, romfilename;
|
||||
|
||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOPinsIn = 0;
|
||||
assign UARTSin = 1;
|
||||
assign HREADYEXT = 1;
|
||||
assign HRESPEXT = 0;
|
||||
assign HRDATAEXT = 0;
|
||||
|
||||
wallypipelinedsoc dut(.*);
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32);
|
||||
localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);
|
||||
|
||||
initial
|
||||
begin
|
||||
test = 0;
|
||||
totalerrors = 0;
|
||||
testadr = 0;
|
||||
// fill memory with defined values to reduce Xs in simulation
|
||||
// Quick note the memory will need to be initialized. The C library does not
|
||||
// guarantee the initialized reads. For example a strcmp can read 6 byte
|
||||
// strings, but uses a load double to read them in. If the last 2 bytes are
|
||||
// not initialized the compare results in an 'x' which propagates through
|
||||
// the design.
|
||||
if (`XLEN == 32) meminit = 32'hFEDC0123;
|
||||
else meminit = 64'hFEDCBA9876543210;
|
||||
// *** broken because DTIM also drives RAM
|
||||
if (`TESTSBP) begin
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
|
||||
dut.uncore.dtim.RAM[i] = meminit;
|
||||
end
|
||||
end
|
||||
// read test vectors into memory
|
||||
bootroot = "../../imperas-riscv-tests/";
|
||||
tvroot = "/home/harris/github/riscv-arch-test/";
|
||||
memfilename = {tvroot, "work/", tests[test], ".elf.memfile"};
|
||||
// romfilename = {bootroot, "imperas-boottim.txt"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
// $readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
|
||||
ProgramAddrMapFile = {tvroot, "work/", tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {tvroot, "work/", tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset = 1; # 42; reset = 0;
|
||||
end
|
||||
|
||||
// generate clock to sequence tests
|
||||
always
|
||||
begin
|
||||
clk = 1; # 5; clk = 0; # 5;
|
||||
end
|
||||
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
begin
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if (dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
if (DCacheFlushDone) begin
|
||||
//$display("Code ended with ecall with gp = 1");
|
||||
|
||||
#600; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
sig32[i] = 'bx;
|
||||
end
|
||||
|
||||
// read signature, reformat in 64 bits if necessary
|
||||
signame = {tvroot, "work/", tests[test], ".signature.output"};
|
||||
$readmemh(signame, sig32);
|
||||
i = 0;
|
||||
while (i < SIGNATURESIZE) begin
|
||||
if (`XLEN == 32) begin
|
||||
signature[i] = sig32[i];
|
||||
i = i+1;
|
||||
end else begin
|
||||
signature[i/2] = {sig32[i+1], sig32[i]};
|
||||
i = i + 2;
|
||||
end
|
||||
if (sig32[i-1] === 'bx) begin
|
||||
if (i == 1) begin
|
||||
i = SIGNATURESIZE+1; // flag empty file
|
||||
$display(" Error: empty test file");
|
||||
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
|
||||
end
|
||||
end
|
||||
|
||||
// Check errors
|
||||
errors = (i == SIGNATURESIZE+1); // error if file is empty
|
||||
i = 0;
|
||||
testadr = (`TIM_BASE+tests[test+1].atohex())/(`XLEN/8);
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
if (signature[i] !== dut.uncore.dtim.RAM[testadr+i] &&
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
// kind of hacky test for garbage right now
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
|
||||
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.dtim.RAM[testadr+i], signature[i]);
|
||||
$stop;//***debug
|
||||
end
|
||||
end
|
||||
i = i + 1;
|
||||
end
|
||||
/* verilator lint_on INFINITELOOP */
|
||||
if (errors == 0) begin
|
||||
$display("%s succeeded. Brilliant!!!", tests[test]);
|
||||
end
|
||||
else begin
|
||||
$display("%s failed with %d errors. :(", tests[test], errors);
|
||||
totalerrors = totalerrors+1;
|
||||
end
|
||||
test = test + 2;
|
||||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||
$stop;
|
||||
end
|
||||
else begin
|
||||
memfilename = {tvroot, "work/",tests[test], ".elf.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
$display("Read memfile %s", memfilename);
|
||||
ProgramAddrMapFile = {tvroot, "work/", tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {tvroot, "work/", tests[test], ".elf.objdump.lab"};
|
||||
reset = 1; # 17; reset = 0;
|
||||
end
|
||||
end
|
||||
end // always @ (negedge clk)
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1) begin : FunctionName
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
.clk(clk),
|
||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
// flush cache and halt on infinite loop at end of riscv-arch-test
|
||||
assign DCacheFlushStart = dut.hart.ifu.InstrM == 32'h6f && dut.hart.ieu.c.InstrValidM;
|
||||
// assign DCacheFlushStart = dut.hart.lsu.dcache.MemPAdrM[31:0] == 32'h80008000 &
|
||||
// dut.hart.lsu.dcache.MemRWM == 2'b01;
|
||||
|
||||
/* assign DCacheFlushStart = dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1));
|
||||
*/
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
|
||||
generate
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module riscvassertions();
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float");
|
||||
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`TIM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
/* verilator lint_on STMTDLY */
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
module DCacheFlushFSM
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
genvar adr;
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
generate
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.logblockbytelen(logblockbytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
integer i, j, k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
flop #(1) doneReg(.clk(clk),
|
||||
.d(start),
|
||||
.q(done));
|
||||
|
||||
endmodule
|
||||
|
||||
module copyShadow
|
||||
#(parameter tagstart, logblockbytelen)
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [`XLEN-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [`XLEN-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
output logic CacheDirty);
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(start) begin
|
||||
CacheTag = tag;
|
||||
CacheValid = valid;
|
||||
CacheDirty = dirty;
|
||||
CacheData = data;
|
||||
CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8));
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,872 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// testbench-imperas.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Wally Testbench and helper modules
|
||||
// Applies test programs from the Imperas suite
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module testbench();
|
||||
parameter DEBUG = 0;
|
||||
parameter TESTSPERIPH = 0; // set to 0 for regression
|
||||
parameter TESTSPRIV = 0; // set to 0 for regression
|
||||
|
||||
logic clk;
|
||||
logic reset;
|
||||
|
||||
parameter SIGNATURESIZE = 5000000;
|
||||
|
||||
int test, i, errors, totalerrors;
|
||||
logic [31:0] sig32[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] testadr;
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
logic [`XLEN-1:0] meminit;
|
||||
|
||||
string tests32mmu[] = '{
|
||||
"rv32mmu/WALLY-MMU-SV32", "3000"
|
||||
//"rv32mmu/WALLY-PMP", "3000",
|
||||
//"rv32mmu/WALLY-PMA", "3000"
|
||||
};
|
||||
|
||||
string tests64mmu[] = '{
|
||||
"rv64mmu/WALLY-MMU-SV48", "3000",
|
||||
"rv64mmu/WALLY-MMU-SV39", "3000",
|
||||
"rv64mmu/WALLY-PMP", "3000"
|
||||
//"rv64mmu/WALLY-PMA", "3000"
|
||||
};
|
||||
|
||||
|
||||
string tests32f[] = '{
|
||||
"rv32f/I-FADD-S-01", "2000",
|
||||
"rv32f/I-FCLASS-S-01", "2000",
|
||||
"rv32f/I-FCVT-S-W-01", "2000",
|
||||
"rv32f/I-FCVT-S-WU-01", "2000",
|
||||
"rv32f/I-FCVT-W-S-01", "2000",
|
||||
"rv32f/I-FCVT-WU-S-01", "2000",
|
||||
"rv32f/I-FDIV-S-01", "2000",
|
||||
"rv32f/I-FEQ-S-01", "2000",
|
||||
"rv32f/I-FLE-S-01", "2000",
|
||||
"rv32f/I-FLT-S-01", "2000",
|
||||
"rv32f/I-FMADD-S-01", "2000",
|
||||
"rv32f/I-FMAX-S-01", "2000",
|
||||
"rv32f/I-FMIN-S-01", "2000",
|
||||
"rv32f/I-FMSUB-S-01", "2000",
|
||||
"rv32f/I-FMUL-S-01", "2000",
|
||||
"rv32f/I-FMV-W-X-01", "2000",
|
||||
"rv32f/I-FMV-X-W-01", "2000",
|
||||
"rv32f/I-FNMADD-S-01", "2000",
|
||||
"rv32f/I-FNMSUB-S-01", "2000",
|
||||
"rv32f/I-FSGNJ-S-01", "2000",
|
||||
"rv32f/I-FSGNJN-S-01", "2000",
|
||||
"rv32f/I-FSGNJX-S-01", "2000",
|
||||
"rv32f/I-FSQRT-S-01", "2000",
|
||||
"rv32f/I-FSW-01", "2000",
|
||||
"rv32f/I-FLW-01", "2110",
|
||||
"rv32f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
string tests64f[] = '{
|
||||
"rv64f/I-FLW-01", "2110",
|
||||
"rv64f/I-FMV-W-X-01", "2000",
|
||||
"rv64f/I-FMV-X-W-01", "2000",
|
||||
"rv64f/I-FSW-01", "2000",
|
||||
"rv64f/I-FCLASS-S-01", "2000",
|
||||
"rv64f/I-FADD-S-01", "2000",
|
||||
// "rv64f/I-FCVT-S-L-01", "2000",
|
||||
// "rv64f/I-FCVT-S-LU-01", "2000",
|
||||
// "rv64f/I-FCVT-S-W-01", "2000",
|
||||
// "rv64f/I-FCVT-S-WU-01", "2000",
|
||||
"rv64f/I-FCVT-L-S-01", "2000",
|
||||
"rv64f/I-FCVT-LU-S-01", "2000",
|
||||
"rv64f/I-FCVT-W-S-01", "2000",
|
||||
"rv64f/I-FCVT-WU-S-01", "2000",
|
||||
"rv64f/I-FDIV-S-01", "2000",
|
||||
"rv64f/I-FEQ-S-01", "2000",
|
||||
"rv64f/I-FLE-S-01", "2000",
|
||||
"rv64f/I-FLT-S-01", "2000",
|
||||
"rv64f/I-FMADD-S-01", "2000",
|
||||
"rv64f/I-FMAX-S-01", "2000",
|
||||
"rv64f/I-FMIN-S-01", "2000",
|
||||
"rv64f/I-FMSUB-S-01", "2000",
|
||||
"rv64f/I-FMUL-S-01", "2000",
|
||||
"rv64f/I-FNMADD-S-01", "2000",
|
||||
"rv64f/I-FNMSUB-S-01", "2000",
|
||||
"rv64f/I-FSGNJ-S-01", "2000",
|
||||
"rv64f/I-FSGNJN-S-01", "2000",
|
||||
"rv64f/I-FSGNJX-S-01", "2000",
|
||||
"rv64f/I-FSQRT-S-01", "2000",
|
||||
"rv64f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
string tests64d[] = '{
|
||||
"rv64d/I-FSD-01", "2000",
|
||||
"rv64d/I-FLD-01", "2420",
|
||||
"rv64d/I-FMV-X-D-01", "2000",
|
||||
"rv64d/I-FMV-D-X-01", "2000",
|
||||
"rv64d/I-FDIV-D-01", "2000",
|
||||
"rv64d/I-FNMADD-D-01", "2000",
|
||||
"rv64d/I-FNMSUB-D-01", "2000",
|
||||
"rv64d/I-FMSUB-D-01", "2000",
|
||||
"rv64d/I-FMAX-D-01", "2000",
|
||||
"rv64d/I-FMIN-D-01", "2000",
|
||||
"rv64d/I-FLE-D-01", "2000",
|
||||
"rv64d/I-FLT-D-01", "2000",
|
||||
"rv64d/I-FEQ-D-01", "2000",
|
||||
"rv64d/I-FADD-D-01", "2000",
|
||||
"rv64d/I-FCLASS-D-01", "2000",
|
||||
"rv64d/I-FMADD-D-01", "2000",
|
||||
"rv64d/I-FMUL-D-01", "2000",
|
||||
"rv64d/I-FSGNJ-D-01", "2000",
|
||||
"rv64d/I-FSGNJN-D-01", "2000",
|
||||
"rv64d/I-FSGNJX-D-01", "2000",
|
||||
"rv64d/I-FSQRT-D-01", "2000",
|
||||
"rv64d/I-FSUB-D-01", "2000",
|
||||
// "rv64d/I-FCVT-D-L-01", "2000",
|
||||
// "rv64d/I-FCVT-D-LU-01", "2000",
|
||||
"rv64d/I-FCVT-D-S-01", "2000",
|
||||
// "rv64d/I-FCVT-D-W-01", "2000",
|
||||
// "rv64d/I-FCVT-D-WU-01", "2000",
|
||||
"rv64d/I-FCVT-L-D-01", "2000",
|
||||
"rv64d/I-FCVT-LU-D-01", "2000",
|
||||
"rv64d/I-FCVT-S-D-01", "2000",
|
||||
"rv64d/I-FCVT-W-D-01", "2000",
|
||||
"rv64d/I-FCVT-WU-D-01", "2000"
|
||||
};
|
||||
|
||||
string tests64a[] = '{
|
||||
"rv64a/WALLY-AMO", "2110",
|
||||
"rv64a/WALLY-LRSC", "2110"
|
||||
};
|
||||
|
||||
string tests64m[] = '{
|
||||
"rv64m/I-REMUW-01", "3000",
|
||||
"rv64m/I-REMW-01", "3000",
|
||||
"rv64m/I-DIVUW-01", "3000",
|
||||
"rv64m/I-DIVW-01", "3000",
|
||||
"rv64m/I-MUL-01", "3000",
|
||||
"rv64m/I-MULH-01", "3000",
|
||||
"rv64m/I-MULHSU-01", "3000",
|
||||
"rv64m/I-MULHU-01", "3000",
|
||||
"rv64m/I-MULW-01", "3000",
|
||||
"rv64m/I-DIV-01", "3000",
|
||||
"rv64m/I-DIVU-01", "3000",
|
||||
"rv64m/I-REM-01", "3000",
|
||||
"rv64m/I-REMU-01", "3000"
|
||||
};
|
||||
|
||||
string tests64ic[] = '{
|
||||
"rv64ic/I-C-ADD-01", "3000",
|
||||
"rv64ic/I-C-ADDI-01", "3000",
|
||||
"rv64ic/I-C-ADDIW-01", "3000",
|
||||
"rv64ic/I-C-ADDW-01", "3000",
|
||||
"rv64ic/I-C-AND-01", "3000",
|
||||
"rv64ic/I-C-ANDI-01", "3000",
|
||||
"rv64ic/I-C-BEQZ-01", "3000",
|
||||
"rv64ic/I-C-BNEZ-01", "3000",
|
||||
"rv64ic/I-C-EBREAK-01", "2000",
|
||||
"rv64ic/I-C-J-01", "3000",
|
||||
"rv64ic/I-C-JALR-01", "4000",
|
||||
"rv64ic/I-C-JR-01", "4000",
|
||||
"rv64ic/I-C-LD-01", "3420",
|
||||
"rv64ic/I-C-LDSP-01", "3420",
|
||||
"rv64ic/I-C-LI-01", "3000",
|
||||
"rv64ic/I-C-LUI-01", "2000",
|
||||
"rv64ic/I-C-LW-01", "3110",
|
||||
"rv64ic/I-C-LWSP-01", "3110",
|
||||
"rv64ic/I-C-MV-01", "3000",
|
||||
"rv64ic/I-C-NOP-01", "2000",
|
||||
"rv64ic/I-C-OR-01", "3000",
|
||||
"rv64ic/I-C-SD-01", "3000",
|
||||
"rv64ic/I-C-SDSP-01", "3000",
|
||||
"rv64ic/I-C-SLLI-01", "3000",
|
||||
"rv64ic/I-C-SRAI-01", "3000",
|
||||
"rv64ic/I-C-SRLI-01", "3000",
|
||||
"rv64ic/I-C-SUB-01", "3000",
|
||||
"rv64ic/I-C-SUBW-01", "3000",
|
||||
"rv64ic/I-C-SW-01", "3000",
|
||||
"rv64ic/I-C-SWSP-01", "3000",
|
||||
"rv64ic/I-C-XOR-01", "3000"
|
||||
};
|
||||
|
||||
string tests64iNOc[] = {
|
||||
"rv64i/I-MISALIGN_JMP-01","2000"
|
||||
};
|
||||
|
||||
string tests64i[] = '{
|
||||
//"rv64i/WALLY-PIPELINE-100K", "f7ff0",
|
||||
"rv64i/I-ADD-01", "3000",
|
||||
"rv64i/I-ADDI-01", "3000",
|
||||
"rv64i/I-ADDIW-01", "3000",
|
||||
"rv64i/I-ADDW-01", "3000",
|
||||
"rv64i/I-AND-01", "3000",
|
||||
"rv64i/I-ANDI-01", "3000",
|
||||
"rv64i/I-AUIPC-01", "3000",
|
||||
"rv64i/I-BEQ-01", "4000",
|
||||
"rv64i/I-BGE-01", "4000",
|
||||
"rv64i/I-BGEU-01", "4000",
|
||||
"rv64i/I-BLT-01", "4000",
|
||||
"rv64i/I-BLTU-01", "4000",
|
||||
"rv64i/I-BNE-01", "4000",
|
||||
"rv64i/I-DELAY_SLOTS-01", "2000",
|
||||
"rv64i/I-EBREAK-01", "2000",
|
||||
"rv64i/I-ECALL-01", "2000",
|
||||
"rv64i/I-ENDIANESS-01", "2010",
|
||||
"rv64i/I-IO-01", "2050",
|
||||
"rv64i/I-JAL-01", "3000",
|
||||
"rv64i/I-JALR-01", "4000",
|
||||
"rv64i/I-LB-01", "4020",
|
||||
"rv64i/I-LBU-01", "4020",
|
||||
"rv64i/I-LD-01", "4420",
|
||||
"rv64i/I-LH-01", "4050",
|
||||
"rv64i/I-LHU-01", "4050",
|
||||
"rv64i/I-LUI-01", "2000",
|
||||
"rv64i/I-LW-01", "4110",
|
||||
"rv64i/I-LWU-01", "4110",
|
||||
"rv64i/I-MISALIGN_LDST-01", "2010",
|
||||
"rv64i/I-NOP-01", "2000",
|
||||
"rv64i/I-OR-01", "3000",
|
||||
"rv64i/I-ORI-01", "3000",
|
||||
"rv64i/I-RF_size-01", "2000",
|
||||
"rv64i/I-RF_width-01", "2000",
|
||||
"rv64i/I-RF_x0-01", "2010",
|
||||
"rv64i/I-SB-01", "4000",
|
||||
"rv64i/I-SD-01", "4000",
|
||||
"rv64i/I-SH-01", "4000",
|
||||
"rv64i/I-SLL-01", "3000",
|
||||
"rv64i/I-SLLI-01", "3000",
|
||||
"rv64i/I-SLLIW-01", "3000",
|
||||
"rv64i/I-SLLW-01", "3000",
|
||||
"rv64i/I-SLT-01", "3000",
|
||||
"rv64i/I-SLTI-01", "3000",
|
||||
"rv64i/I-SLTIU-01", "3000",
|
||||
"rv64i/I-SLTU-01", "3000",
|
||||
"rv64i/I-SRA-01", "3000",
|
||||
"rv64i/I-SRAI-01", "3000",
|
||||
"rv64i/I-SRAIW-01", "3000",
|
||||
"rv64i/I-SRAW-01", "3000",
|
||||
"rv64i/I-SRL-01", "3000",
|
||||
"rv64i/I-SRLI-01", "3000",
|
||||
"rv64i/I-SRLIW-01", "3000",
|
||||
"rv64i/I-SRLW-01", "3000",
|
||||
"rv64i/I-SUB-01", "3000",
|
||||
"rv64i/I-SUBW-01", "3000",
|
||||
"rv64i/I-SW-01", "4000",
|
||||
"rv64i/I-XOR-01", "3000",
|
||||
"rv64i/I-XORI-01", "3000",
|
||||
"rv64i/WALLY-ADD", "4000",
|
||||
"rv64i/WALLY-SUB", "4000",
|
||||
"rv64i/WALLY-ADDI", "3000",
|
||||
"rv64i/WALLY-ANDI", "3000",
|
||||
"rv64i/WALLY-ORI", "3000",
|
||||
"rv64i/WALLY-XORI", "3000",
|
||||
"rv64i/WALLY-SLTI", "3000",
|
||||
"rv64i/WALLY-SLTIU", "3000",
|
||||
"rv64i/WALLY-SLLI", "3000",
|
||||
"rv64i/WALLY-SRLI", "3000",
|
||||
"rv64i/WALLY-SRAI", "3000",
|
||||
"rv64i/WALLY-JAL", "4000",
|
||||
"rv64i/WALLY-JALR", "3000",
|
||||
"rv64i/WALLY-STORE", "3000",
|
||||
"rv64i/WALLY-ADDIW", "3000",
|
||||
"rv64i/WALLY-SLLIW", "3000",
|
||||
"rv64i/WALLY-SRLIW", "3000",
|
||||
"rv64i/WALLY-SRAIW", "3000",
|
||||
"rv64i/WALLY-ADDW", "4000",
|
||||
"rv64i/WALLY-SUBW", "4000",
|
||||
"rv64i/WALLY-SLLW", "3000",
|
||||
"rv64i/WALLY-SRLW", "3000",
|
||||
"rv64i/WALLY-SRAW", "3000",
|
||||
"rv64i/WALLY-BEQ" ,"5000",
|
||||
"rv64i/WALLY-BNE", "5000 ",
|
||||
"rv64i/WALLY-BLTU", "5000 ",
|
||||
"rv64i/WALLY-BLT", "5000",
|
||||
"rv64i/WALLY-BGE", "5000 ",
|
||||
"rv64i/WALLY-BGEU", "5000 ",
|
||||
"rv64i/WALLY-CSRRW", "4000",
|
||||
"rv64i/WALLY-CSRRS", "4000",
|
||||
"rv64i/WALLY-CSRRC", "5000",
|
||||
"rv64i/WALLY-CSRRWI", "4000",
|
||||
"rv64i/WALLY-CSRRSI", "4000",
|
||||
"rv64i/WALLY-CSRRCI", "4000"
|
||||
};
|
||||
|
||||
string tests32a[] = '{
|
||||
"rv32a/WALLY-AMO", "2110",
|
||||
"rv32a/WALLY-LRSC", "2110"
|
||||
};
|
||||
|
||||
string tests32m[] = '{
|
||||
"rv32m/I-DIVU-01", "2000",
|
||||
"rv32m/I-REMU-01", "2000",
|
||||
"rv32m/I-DIV-01", "2000",
|
||||
"rv32m/I-REM-01", "2000",
|
||||
"rv32m/I-MUL-01", "2000",
|
||||
"rv32m/I-MULH-01", "2000",
|
||||
"rv32m/I-MULHSU-01", "2000",
|
||||
"rv32m/I-MULHU-01", "2000"
|
||||
};
|
||||
|
||||
string tests32ic[] = '{
|
||||
"rv32ic/I-C-ADD-01", "2000",
|
||||
"rv32ic/I-C-ADDI-01", "2000",
|
||||
"rv32ic/I-C-AND-01", "2000",
|
||||
"rv32ic/I-C-ANDI-01", "2000",
|
||||
"rv32ic/I-C-BEQZ-01", "2000",
|
||||
"rv32ic/I-C-BNEZ-01", "2000",
|
||||
"rv32ic/I-C-EBREAK-01", "2000",
|
||||
"rv32ic/I-C-J-01", "2000",
|
||||
"rv32ic/I-C-JALR-01", "3000",
|
||||
"rv32ic/I-C-JR-01", "3000",
|
||||
"rv32ic/I-C-LI-01", "2000",
|
||||
"rv32ic/I-C-LUI-01", "2000",
|
||||
"rv32ic/I-C-LW-01", "2110",
|
||||
"rv32ic/I-C-LWSP-01", "2110",
|
||||
"rv32ic/I-C-MV-01", "2000",
|
||||
"rv32ic/I-C-NOP-01", "2000",
|
||||
"rv32ic/I-C-OR-01", "2000",
|
||||
"rv32ic/I-C-SLLI-01", "2000",
|
||||
"rv32ic/I-C-SRAI-01", "2000",
|
||||
"rv32ic/I-C-SRLI-01", "2000",
|
||||
"rv32ic/I-C-SUB-01", "2000",
|
||||
"rv32ic/I-C-SW-01", "2000",
|
||||
"rv32ic/I-C-SWSP-01", "2000",
|
||||
"rv32ic/I-C-XOR-01", "2000"
|
||||
};
|
||||
|
||||
string tests32iNOc[] = {
|
||||
"rv32i/I-MISALIGN_JMP-01","2000"
|
||||
};
|
||||
|
||||
string tests32i[] = {
|
||||
//"rv32i/WALLY-PIPELINE-100K", "10a800",
|
||||
"rv32i/I-ADD-01", "2000",
|
||||
"rv32i/I-ADDI-01","2000",
|
||||
"rv32i/I-AND-01","2000",
|
||||
"rv32i/I-ANDI-01","2000",
|
||||
"rv32i/I-AUIPC-01","2000",
|
||||
"rv32i/I-BEQ-01","3000",
|
||||
"rv32i/I-BGE-01","3000",
|
||||
"rv32i/I-BGEU-01","3000",
|
||||
"rv32i/I-BLT-01","3000",
|
||||
"rv32i/I-BLTU-01","3000",
|
||||
"rv32i/I-BNE-01","3000",
|
||||
"rv32i/I-DELAY_SLOTS-01","2000",
|
||||
"rv32i/I-EBREAK-01","2000",
|
||||
"rv32i/I-ECALL-01","2000",
|
||||
"rv32i/I-ENDIANESS-01","2010",
|
||||
"rv32i/I-IO-01","2030rv",
|
||||
"rv32i/I-JAL-01","3000",
|
||||
"rv32i/I-JALR-01","3000",
|
||||
"rv32i/I-LB-01","3020",
|
||||
"rv32i/I-LBU-01","3020",
|
||||
"rv32i/I-LH-01","3050",
|
||||
"rv32i/I-LHU-01","3050",
|
||||
"rv32i/I-LUI-01","2000",
|
||||
"rv32i/I-LW-01","3110",
|
||||
"rv32i/I-MISALIGN_LDST-01","2010",
|
||||
"rv32i/I-NOP-01","2000",
|
||||
"rv32i/I-OR-01","2000",
|
||||
"rv32i/I-ORI-01","2000",
|
||||
"rv32i/I-RF_size-01","2000",
|
||||
"rv32i/I-RF_width-01","2000",
|
||||
"rv32i/I-RF_x0-01","2010",
|
||||
"rv32i/I-SB-01","3000",
|
||||
"rv32i/I-SH-01","3000",
|
||||
"rv32i/I-SLL-01","2000",
|
||||
"rv32i/I-SLLI-01","2000",
|
||||
"rv32i/I-SLT-01","2000",
|
||||
"rv32i/I-SLTI-01","2000",
|
||||
"rv32i/I-SLTIU-01","2000",
|
||||
"rv32i/I-SLTU-01","2000",
|
||||
"rv32i/I-SRA-01","2000",
|
||||
"rv32i/I-SRAI-01","2000",
|
||||
"rv32i/I-SRL-01","2000",
|
||||
"rv32i/I-SRLI-01","2000",
|
||||
"rv32i/I-SUB-01","2000",
|
||||
"rv32i/I-SW-01","3000",
|
||||
"rv32i/I-XOR-01","2000",
|
||||
"rv32i/I-XORI-01","2000",
|
||||
"rv32i/WALLY-ADD", "3000",
|
||||
"rv32i/WALLY-SUB", "3000",
|
||||
"rv32i/WALLY-ADDI", "2000",
|
||||
"rv32i/WALLY-ANDI", "2000",
|
||||
"rv32i/WALLY-ORI", "2000",
|
||||
"rv32i/WALLY-XORI", "2000",
|
||||
"rv32i/WALLY-SLTI", "2000",
|
||||
"rv32i/WALLY-SLTIU", "2000",
|
||||
"rv32i/WALLY-SLLI", "2000",
|
||||
"rv32i/WALLY-SRLI", "2000",
|
||||
"rv32i/WALLY-SRAI", "2000",
|
||||
"rv32i/WALLY-LOAD", "11c00",
|
||||
"rv32i/WALLY-SUB", "3000",
|
||||
"rv32i/WALLY-STORE", "2000",
|
||||
"rv32i/WALLY-JAL", "3000",
|
||||
"rv32i/WALLY-JALR", "2000",
|
||||
"rv32i/WALLY-BEQ" ,"4000",
|
||||
"rv32i/WALLY-BNE", "4000 ",
|
||||
"rv32i/WALLY-BLTU", "4000 ",
|
||||
"rv32i/WALLY-BLT", "4000",
|
||||
"rv32i/WALLY-BGE", "4000 ",
|
||||
"rv32i/WALLY-BGEU", "4000 ",
|
||||
"rv32i/WALLY-CSRRW", "3000",
|
||||
"rv32i/WALLY-CSRRS", "3000",
|
||||
"rv32i/WALLY-CSRRC", "4000",
|
||||
"rv32i/WALLY-CSRRWI", "3000",
|
||||
"rv32i/WALLY-CSRRSI", "3000",
|
||||
"rv32i/WALLY-CSRRCI", "3000"
|
||||
};
|
||||
|
||||
string testsBP64[] = '{
|
||||
"rv64BP/simple", "10000",
|
||||
"rv64BP/mmm", "1000000",
|
||||
"rv64BP/linpack_bench", "1000000",
|
||||
"rv64BP/sieve", "1000000",
|
||||
"rv64BP/qsort", "1000000",
|
||||
"rv64BP/dhrystone", "1000000"
|
||||
};
|
||||
|
||||
string tests64p[] = '{
|
||||
"rv64p/WALLY-MSTATUS", "2000",
|
||||
"rv64p/WALLY-MCAUSE", "3000",
|
||||
"rv64p/WALLY-SCAUSE", "2000",
|
||||
"rv64p/WALLY-MEPC", "5000",
|
||||
"rv64p/WALLY-SEPC", "4000",
|
||||
"rv64p/WALLY-MTVAL", "6000",
|
||||
"rv64p/WALLY-STVAL", "4000",
|
||||
"rv64p/WALLY-MTVEC", "2000",
|
||||
"rv64p/WALLY-STVEC", "2000",
|
||||
"rv64p/WALLY-MARCHID", "4000",
|
||||
"rv64p/WALLY-MIMPID", "4000",
|
||||
"rv64p/WALLY-MHARTID", "4000",
|
||||
"rv64p/WALLY-MVENDORID", "4000",
|
||||
"rv64p/WALLY-MIE", "3000",
|
||||
"rv64p/WALLY-MEDELEG", "4000",
|
||||
"rv64p/WALLY-IP", "2000",
|
||||
"rv64p/WALLY-CSR-PERMISSIONS-M", "5000",
|
||||
"rv64p/WALLY-CSR-PERMISSIONS-S", "3000"
|
||||
};
|
||||
|
||||
string tests32p[] = '{
|
||||
"rv32p/WALLY-MSTATUS", "2000",
|
||||
"rv32p/WALLY-MCAUSE", "3000",
|
||||
"rv32p/WALLY-SCAUSE", "2000",
|
||||
"rv32p/WALLY-MEPC", "5000",
|
||||
"rv32p/WALLY-SEPC", "4000",
|
||||
"rv32p/WALLY-MTVAL", "5000",
|
||||
"rv32p/WALLY-STVAL", "4000",
|
||||
"rv32p/WALLY-MARCHID", "4000",
|
||||
"rv32p/WALLY-MIMPID", "4000",
|
||||
"rv32p/WALLY-MHARTID", "4000",
|
||||
"rv32p/WALLY-MVENDORID", "4000",
|
||||
"rv32p/WALLY-MTVEC", "2000",
|
||||
"rv32p/WALLY-STVEC", "2000",
|
||||
"rv32p/WALLY-MIE", "3000",
|
||||
"rv32p/WALLY-MEDELEG", "4000",
|
||||
"rv32p/WALLY-IP", "3000",
|
||||
"rv32p/WALLY-CSR-PERMISSIONS-M", "5000",
|
||||
"rv32p/WALLY-CSR-PERMISSIONS-S", "3000"
|
||||
};
|
||||
|
||||
string tests64periph[] = '{
|
||||
"rv64i-periph/WALLY-PERIPH", "2000"
|
||||
};
|
||||
|
||||
string tests32periph[] = '{
|
||||
"rv32i-periph/WALLY-PLIC", "2080"
|
||||
};
|
||||
|
||||
string tests[];
|
||||
string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||
logic [`AHBW-1:0] HRDATAEXT;
|
||||
logic HREADYEXT, HRESPEXT;
|
||||
logic [31:0] HADDR;
|
||||
logic [`AHBW-1:0] HWDATA;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
logic [3:0] HPROT;
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic HCLK, HRESETn;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic DCacheFlushDone, DCacheFlushStart;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
|
||||
// check assertions for a legal configuration
|
||||
riscvassertions riscvassertions();
|
||||
logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
if (`XLEN == 64) begin // RV64
|
||||
if (`TESTSBP) begin
|
||||
tests = testsBP64;
|
||||
// testsbp should not run the other tests. It starts at address 0 rather than
|
||||
// 0x8000_0000, the next if must remain an else if.
|
||||
end else if (TESTSPERIPH)
|
||||
tests = tests64periph;
|
||||
else if (TESTSPRIV)
|
||||
tests = tests64p;
|
||||
else begin
|
||||
tests = {tests64p,tests64i, tests64periph};
|
||||
if (`C_SUPPORTED) tests = {tests, tests64ic};
|
||||
else tests = {tests, tests64iNOc};
|
||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||
if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
|
||||
//if (`A_SUPPORTED) tests = {tests64a, tests};
|
||||
//if (`M_SUPPORTED) tests = {tests64m, tests};
|
||||
end
|
||||
//tests = {tests64a, tests};
|
||||
end else begin // RV32
|
||||
// *** add the 32 bit bp tests
|
||||
if (TESTSPERIPH)
|
||||
tests = tests32periph;
|
||||
else if (TESTSPRIV)
|
||||
tests = tests32p;
|
||||
else begin
|
||||
tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment
|
||||
if (`C_SUPPORTED) tests = {tests, tests32ic};
|
||||
else tests = {tests, tests32iNOc};
|
||||
if (`F_SUPPORTED) tests = {tests32f, tests};
|
||||
if (`MEM_VIRTMEM) tests = {tests32mmu, tests};
|
||||
if (`A_SUPPORTED) tests = {tests32a, tests};
|
||||
if (`M_SUPPORTED) tests = {tests32m, tests};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
string signame, memfilename, romfilename;
|
||||
|
||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOPinsIn = 0;
|
||||
assign UARTSin = 1;
|
||||
assign HREADYEXT = 1;
|
||||
assign HRESPEXT = 0;
|
||||
assign HRDATAEXT = 0;
|
||||
|
||||
wallypipelinedsoc dut(.*);
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32);
|
||||
localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);
|
||||
|
||||
initial
|
||||
begin
|
||||
test = 0;
|
||||
totalerrors = 0;
|
||||
testadr = 0;
|
||||
// fill memory with defined values to reduce Xs in simulation
|
||||
// Quick note the memory will need to be initialized. The C library does not
|
||||
// guarantee the initialized reads. For example a strcmp can read 6 byte
|
||||
// strings, but uses a load double to read them in. If the last 2 bytes are
|
||||
// not initialized the compare results in an 'x' which propagates through
|
||||
// the design.
|
||||
if (`XLEN == 32) meminit = 32'hFEDC0123;
|
||||
else meminit = 64'hFEDCBA9876543210;
|
||||
// *** broken because DTIM also drives RAM
|
||||
if (`TESTSBP) begin
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
|
||||
dut.uncore.dtim.RAM[i] = meminit;
|
||||
end
|
||||
end
|
||||
// read test vectors into memory
|
||||
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
|
||||
// romfilename = {"../../imperas-riscv-tests/imperas-boottim.txt"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
// $readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
|
||||
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset = 1; # 42; reset = 0;
|
||||
end
|
||||
|
||||
// generate clock to sequence tests
|
||||
always
|
||||
begin
|
||||
clk = 1; # 5; clk = 0; # 5;
|
||||
end
|
||||
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
begin
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if (dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
if (DCacheFlushDone) begin
|
||||
//$display("Code ended with ecall with gp = 1");
|
||||
|
||||
#600; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
sig32[i] = 'bx;
|
||||
end
|
||||
|
||||
// read signature, reformat in 64 bits if necessary
|
||||
signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
|
||||
$readmemh(signame, sig32);
|
||||
i = 0;
|
||||
while (i < SIGNATURESIZE) begin
|
||||
if (`XLEN == 32) begin
|
||||
signature[i] = sig32[i];
|
||||
i = i+1;
|
||||
end else begin
|
||||
signature[i/2] = {sig32[i+1], sig32[i]};
|
||||
i = i + 2;
|
||||
end
|
||||
if (sig32[i-1] === 'bx) begin
|
||||
if (i == 1) begin
|
||||
i = SIGNATURESIZE+1; // flag empty file
|
||||
$display(" Error: empty test file");
|
||||
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
|
||||
end
|
||||
end
|
||||
|
||||
// Check errors
|
||||
errors = (i == SIGNATURESIZE+1); // error if file is empty
|
||||
i = 0;
|
||||
testadr = (`TIM_BASE+tests[test+1].atohex())/(`XLEN/8);
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
if (signature[i] !== dut.uncore.dtim.RAM[testadr+i] &&
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
// kind of hacky test for garbage right now
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
|
||||
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.dtim.RAM[testadr+i], signature[i]);
|
||||
//$stop;//***debug
|
||||
end
|
||||
end
|
||||
i = i + 1;
|
||||
end
|
||||
/* verilator lint_on INFINITELOOP */
|
||||
if (errors == 0) begin
|
||||
$display("%s succeeded. Brilliant!!!", tests[test]);
|
||||
end
|
||||
else begin
|
||||
$display("%s failed with %d errors. :(", tests[test], errors);
|
||||
totalerrors = totalerrors+1;
|
||||
end
|
||||
test = test + 2;
|
||||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||
$stop;
|
||||
end
|
||||
else begin
|
||||
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
$display("Read memfile %s", memfilename);
|
||||
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
|
||||
reset = 1; # 17; reset = 0;
|
||||
end
|
||||
end
|
||||
end // always @ (negedge clk)
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1) begin : FunctionName
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
.clk(clk),
|
||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
assign DCacheFlushStart = dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1));
|
||||
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
|
||||
generate
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module riscvassertions();
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`DIV_BITSPERCYCLE == 1 || `DIV_BITSPERCYCLE==2 || `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float");
|
||||
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`TIM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
/* verilator lint_on STMTDLY */
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
module DCacheFlushFSM
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
genvar adr;
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
generate
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.logblockbytelen(logblockbytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
integer i, j, k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
flop #(1) doneReg(.clk(clk),
|
||||
.d(start),
|
||||
.q(done));
|
||||
|
||||
endmodule
|
||||
|
||||
module copyShadow
|
||||
#(parameter tagstart, logblockbytelen)
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [`XLEN-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [`XLEN-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
output logic CacheDirty);
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(start) begin
|
||||
CacheTag = tag;
|
||||
CacheValid = valid;
|
||||
CacheDirty = dirty;
|
||||
CacheData = data;
|
||||
CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8));
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
464
wally-pipelined/testbench/testbench.sv
Normal file
464
wally-pipelined/testbench/testbench.sv
Normal file
@ -0,0 +1,464 @@
|
||||
///////////////////////////////////////////
|
||||
// testbench.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Wally Testbench and helper modules
|
||||
// Applies test programs from the riscv-arch-test and Imperas suites
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
`include "tests.vh"
|
||||
|
||||
module testbench ();
|
||||
parameter TESTSPERIPH = 0; // set to 0 for regression
|
||||
parameter TESTSPRIV = 0; // set to 0 for regression
|
||||
parameter DEBUG=0;
|
||||
parameter TEST="none";
|
||||
|
||||
logic clk;
|
||||
logic reset;
|
||||
|
||||
parameter SIGNATURESIZE = 5000000;
|
||||
|
||||
int test, i, errors, totalerrors;
|
||||
logic [31:0] sig32[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] testadr;
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
logic [`XLEN-1:0] meminit;
|
||||
|
||||
|
||||
string tests[];
|
||||
logic [3:0] dummy;
|
||||
|
||||
string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||
logic [`AHBW-1:0] HRDATAEXT;
|
||||
logic HREADYEXT, HRESPEXT;
|
||||
logic [31:0] HADDR;
|
||||
logic [`AHBW-1:0] HWDATA;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
logic [3:0] HPROT;
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic HCLK, HRESETn;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic DCacheFlushDone, DCacheFlushStart;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
|
||||
// check assertions for a legal configuration
|
||||
riscvassertions riscvassertions();
|
||||
logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
$display("TEST is %s", TEST);
|
||||
tests = '{"empty"};
|
||||
if (`XLEN == 64) begin // RV64
|
||||
case (TEST)
|
||||
"arch64i": tests = arch64i;
|
||||
"arch64priv": tests = arch64priv;
|
||||
"arch64c": if (`C_SUPPORTED) tests = arch64c;
|
||||
"arch64m": if (`M_SUPPORTED) tests = arch64m;
|
||||
"imperas64i": tests = imperas64i;
|
||||
"imperas64p": tests = imperas64p;
|
||||
"imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
|
||||
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
|
||||
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
|
||||
"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
|
||||
"imperas64a": if (`A_SUPPORTED) tests = imperas64a;
|
||||
"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
|
||||
else tests = imperas64iNOc;
|
||||
"testsBP64": tests = testsBP64;
|
||||
// *** add arch f and d tests, peripheral tests
|
||||
endcase
|
||||
end else begin // RV32
|
||||
case (TEST)
|
||||
"arch32i": tests = arch32i;
|
||||
"arch32priv": tests = arch32priv;
|
||||
"arch32c": if (`C_SUPPORTED) tests = arch32c;
|
||||
"arch32m": if (`M_SUPPORTED) tests = arch32m;
|
||||
"imperas32i": tests = imperas32i;
|
||||
"imperas32p": tests = imperas32p;
|
||||
"imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
|
||||
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
|
||||
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
|
||||
"imperas32a": if (`A_SUPPORTED) tests = imperas32a;
|
||||
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
|
||||
else tests = imperas32iNOc;
|
||||
// ***add arch f and d tests
|
||||
endcase
|
||||
end
|
||||
if (tests.size() == 1) begin
|
||||
$display("TEST %s not supported in this configuration", TEST);
|
||||
$stop;
|
||||
end
|
||||
//if (TEST == "arch-64m") //tests = {archtests64m};
|
||||
/* if (`XLEN == 64) begin // RV64
|
||||
if (`TESTSBP) begin
|
||||
tests = testsBP64;
|
||||
// testsbp should not run the other tests. It starts at address 0 rather than
|
||||
// 0x8000_0000, the next if must remain an else if.
|
||||
end else if (TESTSPERIPH)
|
||||
tests = imperastests64periph;
|
||||
else if (TESTSPRIV)
|
||||
tests = imperastests64p;
|
||||
else begin
|
||||
tests = {imperastests64p,imperastests64i, imperastests64periph};
|
||||
if (`C_SUPPORTED) tests = {tests, imperastests64ic};
|
||||
else tests = {tests, imperastests64iNOc};
|
||||
if (`F_SUPPORTED) tests = {imperastests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {imperastests64d, tests};
|
||||
if (`MEM_VIRTMEM) tests = {imperastests64mmu, tests};
|
||||
if (`A_SUPPORTED) tests = {imperastests64a, tests};
|
||||
if (`M_SUPPORTED) tests = {imperastests64m, tests};
|
||||
end
|
||||
//tests = {imperastests64a, tests};
|
||||
end else begin // RV32
|
||||
// *** add the 32 bit bp tests
|
||||
if (TESTSPERIPH)
|
||||
tests = imperastests32periph;
|
||||
else if (TESTSPRIV)
|
||||
tests = imperastests32p;
|
||||
else begin
|
||||
tests = {archtests32i, imperastests32i, imperastests32p};//,imperastests32periph}; *** broken at the moment
|
||||
if (`C_SUPPORTED) tests = {tests, imperastests32ic};
|
||||
else tests = {tests, imperastests32iNOc};
|
||||
if (`F_SUPPORTED) tests = {imperastests32f, tests};
|
||||
if (`MEM_VIRTMEM) tests = {imperastests32mmu, tests};
|
||||
if (`A_SUPPORTED) tests = {imperastests32a, tests};
|
||||
if (`M_SUPPORTED) tests = {imperastests32m, tests};
|
||||
tests = {archtests32i};
|
||||
end
|
||||
end */
|
||||
end
|
||||
|
||||
string signame, memfilename, pathname;
|
||||
|
||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOPinsIn = 0;
|
||||
assign UARTSin = 1;
|
||||
assign HREADYEXT = 1;
|
||||
assign HRESPEXT = 0;
|
||||
assign HRDATAEXT = 0;
|
||||
|
||||
wallypipelinedsoc dut(.*);
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32);
|
||||
localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);
|
||||
|
||||
initial
|
||||
begin
|
||||
test = 1;
|
||||
totalerrors = 0;
|
||||
testadr = 0;
|
||||
// fill memory with defined values to reduce Xs in simulation
|
||||
// Quick note the memory will need to be initialized. The C library does not
|
||||
// guarantee the initialized reads. For example a strcmp can read 6 byte
|
||||
// strings, but uses a load double to read them in. If the last 2 bytes are
|
||||
// not initialized the compare results in an 'x' which propagates through
|
||||
// the design.
|
||||
if (`XLEN == 32) meminit = 32'hFEDC0123;
|
||||
else meminit = 64'hFEDCBA9876543210;
|
||||
// *** broken because DTIM also drives RAM
|
||||
if (`TESTSBP) begin
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
|
||||
dut.uncore.dtim.RAM[i] = meminit;
|
||||
end
|
||||
end
|
||||
// read test vectors into memory
|
||||
if (tests[0] == `IMPERASTEST)
|
||||
pathname = tvpaths[0];
|
||||
else pathname = tvpaths[1];
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset = 1; # 42; reset = 0;
|
||||
end
|
||||
|
||||
// generate clock to sequence tests
|
||||
always
|
||||
begin
|
||||
clk = 1; # 5; clk = 0; # 5;
|
||||
end
|
||||
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (DCacheFlushDone) begin
|
||||
|
||||
#600; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
sig32[i] = 'bx;
|
||||
end
|
||||
|
||||
// read signature, reformat in 64 bits if necessary
|
||||
signame = {pathname, tests[test], ".signature.output"};
|
||||
$readmemh(signame, sig32);
|
||||
i = 0;
|
||||
while (i < SIGNATURESIZE) begin
|
||||
if (`XLEN == 32) begin
|
||||
signature[i] = sig32[i];
|
||||
i = i+1;
|
||||
end else begin
|
||||
signature[i/2] = {sig32[i+1], sig32[i]};
|
||||
i = i + 2;
|
||||
end
|
||||
if (sig32[i-1] === 'bx) begin
|
||||
if (i == 1) begin
|
||||
i = SIGNATURESIZE+1; // flag empty file
|
||||
$display(" Error: empty test file");
|
||||
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
|
||||
end
|
||||
end
|
||||
|
||||
// Check errors
|
||||
errors = (i == SIGNATURESIZE+1); // error if file is empty
|
||||
i = 0;
|
||||
testadr = (`TIM_BASE+tests[test+1].atohex())/(`XLEN/8);
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
if (signature[i] !== dut.uncore.dtim.RAM[testadr+i] &&
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
// kind of hacky test for garbage right now
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
|
||||
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.dtim.RAM[testadr+i], signature[i]);
|
||||
$stop;//***debug
|
||||
end
|
||||
end
|
||||
i = i + 1;
|
||||
end
|
||||
/* verilator lint_on INFINITELOOP */
|
||||
if (errors == 0) begin
|
||||
$display("%s succeeded. Brilliant!!!", tests[test]);
|
||||
end
|
||||
else begin
|
||||
$display("%s failed with %d errors. :(", tests[test], errors);
|
||||
totalerrors = totalerrors+1;
|
||||
end
|
||||
test = test + 2;
|
||||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||
$stop;
|
||||
end
|
||||
else begin
|
||||
//pathname = tvpaths[tests[0]];
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset = 1; # 17; reset = 0;
|
||||
end
|
||||
end
|
||||
end // always @ (negedge clk)
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1) begin : FunctionName
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
.clk(clk),
|
||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
// Termination condition
|
||||
// terminate on a specific ECALL for Imperas tests, or on a jump to self infinite loop for RISC-V Arch tests
|
||||
assign DCacheFlushStart = dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1)) ||
|
||||
dut.hart.ifu.InstrM == 32'h6f && dut.hart.ieu.c.InstrValidM;
|
||||
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
|
||||
generate
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module riscvassertions();
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`DIV_BITSPERCYCLE == 1 || `DIV_BITSPERCYCLE==2 || `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float");
|
||||
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`TIM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
/* verilator lint_on STMTDLY */
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
module DCacheFlushFSM
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
genvar adr;
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
generate
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.logblockbytelen(logblockbytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
integer i, j, k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
flop #(1) doneReg(.clk(clk),
|
||||
.d(start),
|
||||
.q(done));
|
||||
|
||||
endmodule
|
||||
|
||||
module copyShadow
|
||||
#(parameter tagstart, logblockbytelen)
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [`XLEN-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [`XLEN-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
output logic CacheDirty);
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(start) begin
|
||||
CacheTag = tag;
|
||||
CacheValid = valid;
|
||||
CacheDirty = dirty;
|
||||
CacheData = data;
|
||||
CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8));
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
744
wally-pipelined/testbench/tests.vh
Normal file
744
wally-pipelined/testbench/tests.vh
Normal file
@ -0,0 +1,744 @@
|
||||
///////////////////////////////////////////
|
||||
// tests.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 7 October 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: List of tests to apply
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`define IMPERASTEST "0"
|
||||
`define RISCVARCHTEST "1"
|
||||
|
||||
string tvpaths[] = '{
|
||||
"../../imperas-riscv-tests/work/",
|
||||
"/home/harris/github/riscv-arch-test/work/"
|
||||
};
|
||||
|
||||
string imperas32mmu[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32mmu/WALLY-MMU-SV32", "3000"
|
||||
//"rv32mmu/WALLY-PMA", "3000",
|
||||
//"rv32mmu/WALLY-PMA", "3000"
|
||||
};
|
||||
|
||||
string imperas64mmu[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64mmu/WALLY-MMU-SV48", "3000",
|
||||
"rv64mmu/WALLY-MMU-SV39", "3000"
|
||||
//"rv64mmu/WALLY-PMA", "3000",
|
||||
//"rv64mmu/WALLY-PMA", "3000"
|
||||
};
|
||||
|
||||
|
||||
string imperas32f[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32f/I-FADD-S-01", "2000",
|
||||
"rv32f/I-FCLASS-S-01", "2000",
|
||||
"rv32f/I-FCVT-S-W-01", "2000",
|
||||
"rv32f/I-FCVT-S-WU-01", "2000",
|
||||
"rv32f/I-FCVT-W-S-01", "2000",
|
||||
"rv32f/I-FCVT-WU-S-01", "2000",
|
||||
"rv32f/I-FDIV-S-01", "2000",
|
||||
"rv32f/I-FEQ-S-01", "2000",
|
||||
"rv32f/I-FLE-S-01", "2000",
|
||||
"rv32f/I-FLT-S-01", "2000",
|
||||
"rv32f/I-FMADD-S-01", "2000",
|
||||
"rv32f/I-FMAX-S-01", "2000",
|
||||
"rv32f/I-FMIN-S-01", "2000",
|
||||
"rv32f/I-FMSUB-S-01", "2000",
|
||||
"rv32f/I-FMUL-S-01", "2000",
|
||||
"rv32f/I-FMV-W-X-01", "2000",
|
||||
"rv32f/I-FMV-X-W-01", "2000",
|
||||
"rv32f/I-FNMADD-S-01", "2000",
|
||||
"rv32f/I-FNMSUB-S-01", "2000",
|
||||
"rv32f/I-FSGNJ-S-01", "2000",
|
||||
"rv32f/I-FSGNJN-S-01", "2000",
|
||||
"rv32f/I-FSGNJX-S-01", "2000",
|
||||
"rv32f/I-FSQRT-S-01", "2000",
|
||||
"rv32f/I-FSW-01", "2000",
|
||||
"rv32f/I-FLW-01", "2110",
|
||||
"rv32f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
string imperas64f[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64f/I-FLW-01", "2110",
|
||||
"rv64f/I-FMV-W-X-01", "2000",
|
||||
"rv64f/I-FMV-X-W-01", "2000",
|
||||
"rv64f/I-FSW-01", "2000",
|
||||
"rv64f/I-FCLASS-S-01", "2000",
|
||||
"rv64f/I-FADD-S-01", "2000",
|
||||
// "rv64f/I-FCVT-S-L-01", "2000",
|
||||
// "rv64f/I-FCVT-S-LU-01", "2000",
|
||||
// "rv64f/I-FCVT-S-W-01", "2000",
|
||||
// "rv64f/I-FCVT-S-WU-01", "2000",
|
||||
"rv64f/I-FCVT-L-S-01", "2000",
|
||||
"rv64f/I-FCVT-LU-S-01", "2000",
|
||||
"rv64f/I-FCVT-W-S-01", "2000",
|
||||
"rv64f/I-FCVT-WU-S-01", "2000",
|
||||
"rv64f/I-FDIV-S-01", "2000",
|
||||
"rv64f/I-FEQ-S-01", "2000",
|
||||
"rv64f/I-FLE-S-01", "2000",
|
||||
"rv64f/I-FLT-S-01", "2000",
|
||||
"rv64f/I-FMADD-S-01", "2000",
|
||||
"rv64f/I-FMAX-S-01", "2000",
|
||||
"rv64f/I-FMIN-S-01", "2000",
|
||||
"rv64f/I-FMSUB-S-01", "2000",
|
||||
"rv64f/I-FMUL-S-01", "2000",
|
||||
"rv64f/I-FNMADD-S-01", "2000",
|
||||
"rv64f/I-FNMSUB-S-01", "2000",
|
||||
"rv64f/I-FSGNJ-S-01", "2000",
|
||||
"rv64f/I-FSGNJN-S-01", "2000",
|
||||
"rv64f/I-FSGNJX-S-01", "2000",
|
||||
"rv64f/I-FSQRT-S-01", "2000",
|
||||
"rv64f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
string imperas64d[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64d/I-FSD-01", "2000",
|
||||
"rv64d/I-FLD-01", "2420",
|
||||
"rv64d/I-FMV-X-D-01", "2000",
|
||||
"rv64d/I-FMV-D-X-01", "2000",
|
||||
"rv64d/I-FDIV-D-01", "2000",
|
||||
"rv64d/I-FNMADD-D-01", "2000",
|
||||
"rv64d/I-FNMSUB-D-01", "2000",
|
||||
"rv64d/I-FMSUB-D-01", "2000",
|
||||
"rv64d/I-FMAX-D-01", "2000",
|
||||
"rv64d/I-FMIN-D-01", "2000",
|
||||
"rv64d/I-FLE-D-01", "2000",
|
||||
"rv64d/I-FLT-D-01", "2000",
|
||||
"rv64d/I-FEQ-D-01", "2000",
|
||||
"rv64d/I-FADD-D-01", "2000",
|
||||
"rv64d/I-FCLASS-D-01", "2000",
|
||||
"rv64d/I-FMADD-D-01", "2000",
|
||||
"rv64d/I-FMUL-D-01", "2000",
|
||||
"rv64d/I-FSGNJ-D-01", "2000",
|
||||
"rv64d/I-FSGNJN-D-01", "2000",
|
||||
"rv64d/I-FSGNJX-D-01", "2000",
|
||||
"rv64d/I-FSQRT-D-01", "2000",
|
||||
"rv64d/I-FSUB-D-01", "2000",
|
||||
// "rv64d/I-FCVT-D-L-01", "2000",
|
||||
// "rv64d/I-FCVT-D-LU-01", "2000",
|
||||
"rv64d/I-FCVT-D-S-01", "2000",
|
||||
// "rv64d/I-FCVT-D-W-01", "2000",
|
||||
// "rv64d/I-FCVT-D-WU-01", "2000",
|
||||
"rv64d/I-FCVT-L-D-01", "2000",
|
||||
"rv64d/I-FCVT-LU-D-01", "2000",
|
||||
"rv64d/I-FCVT-S-D-01", "2000",
|
||||
"rv64d/I-FCVT-W-D-01", "2000",
|
||||
"rv64d/I-FCVT-WU-D-01", "2000"
|
||||
};
|
||||
|
||||
string imperas64a[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64a/WALLY-AMO", "2110",
|
||||
"rv64a/WALLY-LRSC", "2110"
|
||||
};
|
||||
|
||||
string imperas64m[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64m/I-REMUW-01", "3000",
|
||||
"rv64m/I-REMW-01", "3000",
|
||||
"rv64m/I-DIVUW-01", "3000",
|
||||
"rv64m/I-DIVW-01", "3000",
|
||||
"rv64m/I-MUL-01", "3000",
|
||||
"rv64m/I-MULH-01", "3000",
|
||||
"rv64m/I-MULHSU-01", "3000",
|
||||
"rv64m/I-MULHU-01", "3000",
|
||||
"rv64m/I-MULW-01", "3000",
|
||||
"rv64m/I-DIV-01", "3000",
|
||||
"rv64m/I-DIVU-01", "3000",
|
||||
"rv64m/I-REM-01", "3000",
|
||||
"rv64m/I-REMU-01", "3000"
|
||||
};
|
||||
|
||||
string imperas64c[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64ic/I-C-ADD-01", "3000",
|
||||
"rv64ic/I-C-ADDI-01", "3000",
|
||||
"rv64ic/I-C-ADDIW-01", "3000",
|
||||
"rv64ic/I-C-ADDW-01", "3000",
|
||||
"rv64ic/I-C-AND-01", "3000",
|
||||
"rv64ic/I-C-ANDI-01", "3000",
|
||||
"rv64ic/I-C-BEQZ-01", "3000",
|
||||
"rv64ic/I-C-BNEZ-01", "3000",
|
||||
"rv64ic/I-C-EBREAK-01", "2000",
|
||||
"rv64ic/I-C-J-01", "3000",
|
||||
"rv64ic/I-C-JALR-01", "4000",
|
||||
"rv64ic/I-C-JR-01", "4000",
|
||||
"rv64ic/I-C-LD-01", "3420",
|
||||
"rv64ic/I-C-LDSP-01", "3420",
|
||||
"rv64ic/I-C-LI-01", "3000",
|
||||
"rv64ic/I-C-LUI-01", "2000",
|
||||
"rv64ic/I-C-LW-01", "3110",
|
||||
"rv64ic/I-C-LWSP-01", "3110",
|
||||
"rv64ic/I-C-MV-01", "3000",
|
||||
"rv64ic/I-C-NOP-01", "2000",
|
||||
"rv64ic/I-C-OR-01", "3000",
|
||||
"rv64ic/I-C-SD-01", "3000",
|
||||
"rv64ic/I-C-SDSP-01", "3000",
|
||||
"rv64ic/I-C-SLLI-01", "3000",
|
||||
"rv64ic/I-C-SRAI-01", "3000",
|
||||
"rv64ic/I-C-SRLI-01", "3000",
|
||||
"rv64ic/I-C-SUB-01", "3000",
|
||||
"rv64ic/I-C-SUBW-01", "3000",
|
||||
"rv64ic/I-C-SW-01", "3000",
|
||||
"rv64ic/I-C-SWSP-01", "3000",
|
||||
"rv64ic/I-C-XOR-01", "3000"
|
||||
};
|
||||
|
||||
string imperas64iNOc[] = {
|
||||
`IMPERASTEST,
|
||||
"rv64i/I-MISALIGN_JMP-01","2000"
|
||||
};
|
||||
|
||||
string imperas64i[] = '{
|
||||
`IMPERASTEST,
|
||||
//"rv64i/WALLY-PIPELINE-100K", "f7ff0",
|
||||
"rv64i/I-ADD-01", "3000",
|
||||
"rv64i/I-ADDI-01", "3000",
|
||||
"rv64i/I-ADDIW-01", "3000",
|
||||
"rv64i/I-ADDW-01", "3000",
|
||||
"rv64i/I-AND-01", "3000",
|
||||
"rv64i/I-ANDI-01", "3000",
|
||||
"rv64i/I-AUIPC-01", "3000",
|
||||
"rv64i/I-BEQ-01", "4000",
|
||||
"rv64i/I-BGE-01", "4000",
|
||||
"rv64i/I-BGEU-01", "4000",
|
||||
"rv64i/I-BLT-01", "4000",
|
||||
"rv64i/I-BLTU-01", "4000",
|
||||
"rv64i/I-BNE-01", "4000",
|
||||
"rv64i/I-DELAY_SLOTS-01", "2000",
|
||||
"rv64i/I-EBREAK-01", "2000",
|
||||
"rv64i/I-ECALL-01", "2000",
|
||||
"rv64i/I-ENDIANESS-01", "2010",
|
||||
"rv64i/I-IO-01", "2050",
|
||||
"rv64i/I-JAL-01", "3000",
|
||||
"rv64i/I-JALR-01", "4000",
|
||||
"rv64i/I-LB-01", "4020",
|
||||
"rv64i/I-LBU-01", "4020",
|
||||
"rv64i/I-LD-01", "4420",
|
||||
"rv64i/I-LH-01", "4050",
|
||||
"rv64i/I-LHU-01", "4050",
|
||||
"rv64i/I-LUI-01", "2000",
|
||||
"rv64i/I-LW-01", "4110",
|
||||
"rv64i/I-LWU-01", "4110",
|
||||
"rv64i/I-MISALIGN_LDST-01", "2010",
|
||||
"rv64i/I-NOP-01", "2000",
|
||||
"rv64i/I-OR-01", "3000",
|
||||
"rv64i/I-ORI-01", "3000",
|
||||
"rv64i/I-RF_size-01", "2000",
|
||||
"rv64i/I-RF_width-01", "2000",
|
||||
"rv64i/I-RF_x0-01", "2010",
|
||||
"rv64i/I-SB-01", "4000",
|
||||
"rv64i/I-SD-01", "4000",
|
||||
"rv64i/I-SH-01", "4000",
|
||||
"rv64i/I-SLL-01", "3000",
|
||||
"rv64i/I-SLLI-01", "3000",
|
||||
"rv64i/I-SLLIW-01", "3000",
|
||||
"rv64i/I-SLLW-01", "3000",
|
||||
"rv64i/I-SLT-01", "3000",
|
||||
"rv64i/I-SLTI-01", "3000",
|
||||
"rv64i/I-SLTIU-01", "3000",
|
||||
"rv64i/I-SLTU-01", "3000",
|
||||
"rv64i/I-SRA-01", "3000",
|
||||
"rv64i/I-SRAI-01", "3000",
|
||||
"rv64i/I-SRAIW-01", "3000",
|
||||
"rv64i/I-SRAW-01", "3000",
|
||||
"rv64i/I-SRL-01", "3000",
|
||||
"rv64i/I-SRLI-01", "3000",
|
||||
"rv64i/I-SRLIW-01", "3000",
|
||||
"rv64i/I-SRLW-01", "3000",
|
||||
"rv64i/I-SUB-01", "3000",
|
||||
"rv64i/I-SUBW-01", "3000",
|
||||
"rv64i/I-SW-01", "4000",
|
||||
"rv64i/I-XOR-01", "3000",
|
||||
"rv64i/I-XORI-01", "3000",
|
||||
"rv64i/WALLY-ADD", "4000",
|
||||
"rv64i/WALLY-SUB", "4000",
|
||||
"rv64i/WALLY-ADDI", "3000",
|
||||
"rv64i/WALLY-ANDI", "3000",
|
||||
"rv64i/WALLY-ORI", "3000",
|
||||
"rv64i/WALLY-XORI", "3000",
|
||||
"rv64i/WALLY-SLTI", "3000",
|
||||
"rv64i/WALLY-SLTIU", "3000",
|
||||
"rv64i/WALLY-SLLI", "3000",
|
||||
"rv64i/WALLY-SRLI", "3000",
|
||||
"rv64i/WALLY-SRAI", "3000",
|
||||
"rv64i/WALLY-JAL", "4000",
|
||||
"rv64i/WALLY-JALR", "3000",
|
||||
"rv64i/WALLY-STORE", "3000",
|
||||
"rv64i/WALLY-ADDIW", "3000",
|
||||
"rv64i/WALLY-SLLIW", "3000",
|
||||
"rv64i/WALLY-SRLIW", "3000",
|
||||
"rv64i/WALLY-SRAIW", "3000",
|
||||
"rv64i/WALLY-ADDW", "4000",
|
||||
"rv64i/WALLY-SUBW", "4000",
|
||||
"rv64i/WALLY-SLLW", "3000",
|
||||
"rv64i/WALLY-SRLW", "3000",
|
||||
"rv64i/WALLY-SRAW", "3000",
|
||||
"rv64i/WALLY-BEQ" ,"5000",
|
||||
"rv64i/WALLY-BNE", "5000 ",
|
||||
"rv64i/WALLY-BLTU", "5000 ",
|
||||
"rv64i/WALLY-BLT", "5000",
|
||||
"rv64i/WALLY-BGE", "5000 ",
|
||||
"rv64i/WALLY-BGEU", "5000 ",
|
||||
"rv64i/WALLY-CSRRW", "4000",
|
||||
"rv64i/WALLY-CSRRS", "4000",
|
||||
"rv64i/WALLY-CSRRC", "5000",
|
||||
"rv64i/WALLY-CSRRWI", "4000",
|
||||
"rv64i/WALLY-CSRRSI", "4000",
|
||||
"rv64i/WALLY-CSRRCI", "4000"
|
||||
};
|
||||
|
||||
string imperas32a[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32a/WALLY-AMO", "2110",
|
||||
"rv32a/WALLY-LRSC", "2110"
|
||||
};
|
||||
|
||||
string imperas32m[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32m/I-DIVU-01", "2000",
|
||||
"rv32m/I-REMU-01", "2000",
|
||||
"rv32m/I-DIV-01", "2000",
|
||||
"rv32m/I-REM-01", "2000",
|
||||
"rv32m/I-MUL-01", "2000",
|
||||
"rv32m/I-MULH-01", "2000",
|
||||
"rv32m/I-MULHSU-01", "2000",
|
||||
"rv32m/I-MULHU-01", "2000"
|
||||
};
|
||||
|
||||
string imperas32c[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32ic/I-C-ADD-01", "2000",
|
||||
"rv32ic/I-C-ADDI-01", "2000",
|
||||
"rv32ic/I-C-AND-01", "2000",
|
||||
"rv32ic/I-C-ANDI-01", "2000",
|
||||
"rv32ic/I-C-BEQZ-01", "2000",
|
||||
"rv32ic/I-C-BNEZ-01", "2000",
|
||||
"rv32ic/I-C-EBREAK-01", "2000",
|
||||
"rv32ic/I-C-J-01", "2000",
|
||||
"rv32ic/I-C-JALR-01", "3000",
|
||||
"rv32ic/I-C-JR-01", "3000",
|
||||
"rv32ic/I-C-LI-01", "2000",
|
||||
"rv32ic/I-C-LUI-01", "2000",
|
||||
"rv32ic/I-C-LW-01", "2110",
|
||||
"rv32ic/I-C-LWSP-01", "2110",
|
||||
"rv32ic/I-C-MV-01", "2000",
|
||||
"rv32ic/I-C-NOP-01", "2000",
|
||||
"rv32ic/I-C-OR-01", "2000",
|
||||
"rv32ic/I-C-SLLI-01", "2000",
|
||||
"rv32ic/I-C-SRAI-01", "2000",
|
||||
"rv32ic/I-C-SRLI-01", "2000",
|
||||
"rv32ic/I-C-SUB-01", "2000",
|
||||
"rv32ic/I-C-SW-01", "2000",
|
||||
"rv32ic/I-C-SWSP-01", "2000",
|
||||
"rv32ic/I-C-XOR-01", "2000"
|
||||
};
|
||||
|
||||
string imperas32iNOc[] = {
|
||||
`IMPERASTEST,
|
||||
"rv32i/I-MISALIGN_JMP-01","2000"
|
||||
};
|
||||
|
||||
string imperas32i[] = {
|
||||
`IMPERASTEST,
|
||||
//"rv32i/WALLY-PIPELINE-100K", "10a800",
|
||||
"rv32i/I-ADD-01", "2000",
|
||||
"rv32i/I-ADDI-01","2000",
|
||||
"rv32i/I-AND-01","2000",
|
||||
"rv32i/I-ANDI-01","2000",
|
||||
"rv32i/I-AUIPC-01","2000",
|
||||
"rv32i/I-BEQ-01","3000",
|
||||
"rv32i/I-BGE-01","3000",
|
||||
"rv32i/I-BGEU-01","3000",
|
||||
"rv32i/I-BLT-01","3000",
|
||||
"rv32i/I-BLTU-01","3000",
|
||||
"rv32i/I-BNE-01","3000",
|
||||
"rv32i/I-DELAY_SLOTS-01","2000",
|
||||
"rv32i/I-EBREAK-01","2000",
|
||||
"rv32i/I-ECALL-01","2000",
|
||||
"rv32i/I-ENDIANESS-01","2010",
|
||||
"rv32i/I-IO-01","2030rv",
|
||||
"rv32i/I-JAL-01","3000",
|
||||
"rv32i/I-JALR-01","3000",
|
||||
"rv32i/I-LB-01","3020",
|
||||
"rv32i/I-LBU-01","3020",
|
||||
"rv32i/I-LH-01","3050",
|
||||
"rv32i/I-LHU-01","3050",
|
||||
"rv32i/I-LUI-01","2000",
|
||||
"rv32i/I-LW-01","3110",
|
||||
"rv32i/I-MISALIGN_LDST-01","2010",
|
||||
"rv32i/I-NOP-01","2000",
|
||||
"rv32i/I-OR-01","2000",
|
||||
"rv32i/I-ORI-01","2000",
|
||||
"rv32i/I-RF_size-01","2000",
|
||||
"rv32i/I-RF_width-01","2000",
|
||||
"rv32i/I-RF_x0-01","2010",
|
||||
"rv32i/I-SB-01","3000",
|
||||
"rv32i/I-SH-01","3000",
|
||||
"rv32i/I-SLL-01","2000",
|
||||
"rv32i/I-SLLI-01","2000",
|
||||
"rv32i/I-SLT-01","2000",
|
||||
"rv32i/I-SLTI-01","2000",
|
||||
"rv32i/I-SLTIU-01","2000",
|
||||
"rv32i/I-SLTU-01","2000",
|
||||
"rv32i/I-SRA-01","2000",
|
||||
"rv32i/I-SRAI-01","2000",
|
||||
"rv32i/I-SRL-01","2000",
|
||||
"rv32i/I-SRLI-01","2000",
|
||||
"rv32i/I-SUB-01","2000",
|
||||
"rv32i/I-SW-01","3000",
|
||||
"rv32i/I-XOR-01","2000",
|
||||
"rv32i/I-XORI-01","2000",
|
||||
"rv32i/WALLY-ADD", "3000",
|
||||
"rv32i/WALLY-SUB", "3000",
|
||||
"rv32i/WALLY-ADDI", "2000",
|
||||
"rv32i/WALLY-ANDI", "2000",
|
||||
"rv32i/WALLY-ORI", "2000",
|
||||
"rv32i/WALLY-XORI", "2000",
|
||||
"rv32i/WALLY-SLTI", "2000",
|
||||
"rv32i/WALLY-SLTIU", "2000",
|
||||
"rv32i/WALLY-SLLI", "2000",
|
||||
"rv32i/WALLY-SRLI", "2000",
|
||||
"rv32i/WALLY-SRAI", "2000",
|
||||
"rv32i/WALLY-LOAD", "11c00",
|
||||
"rv32i/WALLY-SUB", "3000",
|
||||
"rv32i/WALLY-STORE", "2000",
|
||||
"rv32i/WALLY-JAL", "3000",
|
||||
"rv32i/WALLY-JALR", "2000",
|
||||
"rv32i/WALLY-BEQ" ,"4000",
|
||||
"rv32i/WALLY-BNE", "4000 ",
|
||||
"rv32i/WALLY-BLTU", "4000 ",
|
||||
"rv32i/WALLY-BLT", "4000",
|
||||
"rv32i/WALLY-BGE", "4000 ",
|
||||
"rv32i/WALLY-BGEU", "4000 ",
|
||||
"rv32i/WALLY-CSRRW", "3000",
|
||||
"rv32i/WALLY-CSRRS", "3000",
|
||||
"rv32i/WALLY-CSRRC", "4000",
|
||||
"rv32i/WALLY-CSRRWI", "3000",
|
||||
"rv32i/WALLY-CSRRSI", "3000",
|
||||
"rv32i/WALLY-CSRRCI", "3000"
|
||||
};
|
||||
|
||||
string testsBP64[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64BP/simple", "10000",
|
||||
"rv64BP/mmm", "1000000",
|
||||
"rv64BP/linpack_bench", "1000000",
|
||||
"rv64BP/sieve", "1000000",
|
||||
"rv64BP/qsort", "1000000",
|
||||
"rv64BP/dhrystone", "1000000"
|
||||
};
|
||||
|
||||
string imperas64p[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64p/WALLY-MSTATUS", "2000",
|
||||
"rv64p/WALLY-MCAUSE", "3000",
|
||||
"rv64p/WALLY-SCAUSE", "2000",
|
||||
"rv64p/WALLY-MEPC", "5000",
|
||||
"rv64p/WALLY-SEPC", "4000",
|
||||
"rv64p/WALLY-MTVAL", "6000",
|
||||
"rv64p/WALLY-STVAL", "4000",
|
||||
"rv64p/WALLY-MTVEC", "2000",
|
||||
"rv64p/WALLY-STVEC", "2000",
|
||||
"rv64p/WALLY-MARCHID", "4000",
|
||||
"rv64p/WALLY-MIMPID", "4000",
|
||||
"rv64p/WALLY-MHARTID", "4000",
|
||||
"rv64p/WALLY-MVENDORID", "4000",
|
||||
"rv64p/WALLY-MIE", "3000",
|
||||
"rv64p/WALLY-MEDELEG", "4000",
|
||||
"rv64p/WALLY-IP", "2000",
|
||||
"rv64p/WALLY-CSR-PERMISSIONS-M", "5000",
|
||||
"rv64p/WALLY-CSR-PERMISSIONS-S", "3000"
|
||||
};
|
||||
|
||||
string imperas32p[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32p/WALLY-MSTATUS", "2000",
|
||||
"rv32p/WALLY-MCAUSE", "3000",
|
||||
"rv32p/WALLY-SCAUSE", "2000",
|
||||
"rv32p/WALLY-MEPC", "5000",
|
||||
"rv32p/WALLY-SEPC", "4000",
|
||||
"rv32p/WALLY-MTVAL", "5000",
|
||||
"rv32p/WALLY-STVAL", "4000",
|
||||
"rv32p/WALLY-MARCHID", "4000",
|
||||
"rv32p/WALLY-MIMPID", "4000",
|
||||
"rv32p/WALLY-MHARTID", "4000",
|
||||
"rv32p/WALLY-MVENDORID", "4000",
|
||||
"rv32p/WALLY-MTVEC", "2000",
|
||||
"rv32p/WALLY-STVEC", "2000",
|
||||
"rv32p/WALLY-MIE", "3000",
|
||||
"rv32p/WALLY-MEDELEG", "4000",
|
||||
"rv32p/WALLY-IP", "3000",
|
||||
"rv32p/WALLY-CSR-PERMISSIONS-M", "5000",
|
||||
"rv32p/WALLY-CSR-PERMISSIONS-S", "3000"
|
||||
};
|
||||
|
||||
string imperas64periph[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64i-periph/WALLY-PERIPH", "2000"
|
||||
};
|
||||
|
||||
string imperas32periph[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32i-periph/WALLY-PLIC", "2080"
|
||||
};
|
||||
|
||||
|
||||
string arch64priv[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/privilege/ebreak", "2090",
|
||||
"rv64i_m/privilege/ecall", "2090",
|
||||
"rv64i_m/privilege/misalign-beq-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bge-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bgeu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-blt-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bltu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-bne-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-jal-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-ld-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lh-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lhu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lw-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-lwu-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-sd-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-sh-01", "20a0",
|
||||
"rv64i_m/privilege/misalign-sw-01", "20a0",
|
||||
"rv64i_m/privilege/misalign1-jalr-01", "20a0",
|
||||
"rv64i_m/privilege/misalign2-jalr-01", "20a0"
|
||||
};
|
||||
|
||||
string arch64m[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/M/div-01", "9010",
|
||||
"rv64i_m/M/divu-01", "a010",
|
||||
"rv64i_m/M/divuw-01", "a010",
|
||||
"rv64i_m/M/divw-01", "9010",
|
||||
"rv64i_m/M/mul-01", "9010",
|
||||
"rv64i_m/M/mulh-01", "9010",
|
||||
"rv64i_m/M/mulhsu-01", "9010",
|
||||
"rv64i_m/M/mulhu-01", "a010",
|
||||
"rv64i_m/M/mulw-01", "9010",
|
||||
"rv64i_m/M/rem-01", "9010",
|
||||
"rv64i_m/M/remu-01", "a010",
|
||||
"rv64i_m/M/remuw-01", "a010",
|
||||
"rv64i_m/M/remw-01", "9010"
|
||||
};
|
||||
|
||||
string arch64c[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/C/cadd-01", "8010",
|
||||
"rv64i_m/C/caddi-01", "4010",
|
||||
"rv64i_m/C/caddi16sp-01", "2010",
|
||||
"rv64i_m/C/caddi4spn-01", "2010",
|
||||
"rv64i_m/C/caddiw-01", "4010",
|
||||
"rv64i_m/C/caddw-01", "8010",
|
||||
"rv64i_m/C/cand-01", "8010",
|
||||
"rv64i_m/C/candi-01", "4010",
|
||||
"rv64i_m/C/cbeqz-01", "4010",
|
||||
"rv64i_m/C/cbnez-01", "5010",
|
||||
"rv64i_m/C/cebreak-01", "2070",
|
||||
"rv64i_m/C/cj-01", "3010",
|
||||
"rv64i_m/C/cjalr-01", "2010",
|
||||
"rv64i_m/C/cjr-01", "2010",
|
||||
"rv64i_m/C/cld-01", "2010",
|
||||
"rv64i_m/C/cldsp-01", "2010",
|
||||
"rv64i_m/C/cli-01", "2010",
|
||||
"rv64i_m/C/clui-01", "2010",
|
||||
"rv64i_m/C/clw-01", "2010",
|
||||
"rv64i_m/C/clwsp-01", "2010",
|
||||
"rv64i_m/C/cmv-01", "2010",
|
||||
"rv64i_m/C/cnop-01", "2010",
|
||||
"rv64i_m/C/cor-01", "8010",
|
||||
"rv64i_m/C/csd-01", "3010",
|
||||
"rv64i_m/C/csdsp-01", "3010",
|
||||
"rv64i_m/C/cslli-01", "2010",
|
||||
"rv64i_m/C/csrai-01", "2010",
|
||||
"rv64i_m/C/csrli-01", "2010",
|
||||
"rv64i_m/C/csub-01", "8010",
|
||||
"rv64i_m/C/csubw-01", "8010",
|
||||
"rv64i_m/C/csw-01", "3010",
|
||||
"rv64i_m/C/cswsp-01", "3010",
|
||||
"rv64i_m/C/cxor-01", "8010"
|
||||
};
|
||||
|
||||
string arch64i[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/I/add-01", "9010",
|
||||
"rv64i_m/I/addi-01", "6010",
|
||||
"rv64i_m/I/addiw-01", "6010",
|
||||
"rv64i_m/I/addw-01", "9010",
|
||||
"rv64i_m/I/and-01", "9010",
|
||||
"rv64i_m/I/andi-01", "6010",
|
||||
"rv64i_m/I/auipc-01", "2010",
|
||||
"rv64i_m/I/beq-01", "47010",
|
||||
"rv64i_m/I/bge-01", "47010",
|
||||
"rv64i_m/I/bgeu-01", "56010",
|
||||
"rv64i_m/I/blt-01", "4d010",
|
||||
"rv64i_m/I/bltu-01", "57010",
|
||||
"rv64i_m/I/bne-01", "43010",
|
||||
"rv64i_m/I/fence-01", "2010",
|
||||
"rv64i_m/I/jal-01", "122010",
|
||||
"rv64i_m/I/jalr-01", "2010",
|
||||
"rv64i_m/I/lb-align-01", "2010",
|
||||
"rv64i_m/I/lbu-align-01", "2010",
|
||||
"rv64i_m/I/ld-align-01", "2010",
|
||||
"rv64i_m/I/lh-align-01", "2010",
|
||||
"rv64i_m/I/lhu-align-01", "2010",
|
||||
"rv64i_m/I/lui-01", "2010",
|
||||
"rv64i_m/I/lw-align-01", "2010",
|
||||
"rv64i_m/I/lwu-align-01", "2010",
|
||||
"rv64i_m/I/or-01", "9010",
|
||||
"rv64i_m/I/ori-01", "6010",
|
||||
"rv64i_m/I/sb-align-01", "3010",
|
||||
"rv64i_m/I/sd-align-01", "3010",
|
||||
"rv64i_m/I/sh-align-01", "3010",
|
||||
"rv64i_m/I/sll-01", "3010",
|
||||
"rv64i_m/I/slli-01", "2010",
|
||||
"rv64i_m/I/slliw-01", "2010",
|
||||
"rv64i_m/I/sllw-01", "3010",
|
||||
"rv64i_m/I/slt-01", "9010",
|
||||
"rv64i_m/I/slti-01", "6010",
|
||||
"rv64i_m/I/sltiu-01", "6010",
|
||||
"rv64i_m/I/sltu-01", "a010",
|
||||
"rv64i_m/I/sra-01", "3010",
|
||||
"rv64i_m/I/srai-01", "2010",
|
||||
"rv64i_m/I/sraiw-01", "2010",
|
||||
"rv64i_m/I/sraw-01", "3010",
|
||||
"rv64i_m/I/srl-01", "3010",
|
||||
"rv64i_m/I/srli-01", "2010",
|
||||
"rv64i_m/I/srliw-01", "2010",
|
||||
"rv64i_m/I/srlw-01", "3010",
|
||||
"rv64i_m/I/sub-01", "9010",
|
||||
"rv64i_m/I/subw-01", "9010",
|
||||
"rv64i_m/I/sw-align-01", "3010",
|
||||
"rv64i_m/I/xor-01", "9010",
|
||||
"rv64i_m/I/xori-01", "6010"
|
||||
};
|
||||
|
||||
string arch32priv[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/privilege/ebreak", "2070",
|
||||
"rv32i_m/privilege/ecall", "2070",
|
||||
"rv32i_m/privilege/misalign-beq-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bge-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bgeu-01", "2080",
|
||||
"rv32i_m/privilege/misalign-blt-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bltu-01", "2080",
|
||||
"rv32i_m/privilege/misalign-bne-01", "2080",
|
||||
"rv32i_m/privilege/misalign-jal-01", "2080",
|
||||
"rv32i_m/privilege/misalign-lh-01", "2080",
|
||||
"rv32i_m/privilege/misalign-lhu-01", "2080",
|
||||
"rv32i_m/privilege/misalign-lw-01", "2080",
|
||||
"rv32i_m/privilege/misalign-sh-01", "2080",
|
||||
"rv32i_m/privilege/misalign-sw-01", "2080",
|
||||
"rv32i_m/privilege/misalign1-jalr-01", "2080",
|
||||
"rv32i_m/privilege/misalign2-jalr-01", "2080"
|
||||
};
|
||||
|
||||
string arch32m[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/M/div-01", "5010",
|
||||
"rv32i_m/M/divu-01", "5010",
|
||||
"rv32i_m/M/mul-01", "5010",
|
||||
"rv32i_m/M/mulh-01", "5010",
|
||||
"rv32i_m/M/mulhsu-01", "5010",
|
||||
"rv32i_m/M/mulhu-01", "5010",
|
||||
"rv32i_m/M/rem-01", "5010",
|
||||
"rv32i_m/M/remu-01", "5010"
|
||||
};
|
||||
|
||||
string arch32c[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/C/cadd-01", "4010",
|
||||
"rv32i_m/C/caddi-01", "3010",
|
||||
"rv32i_m/C/caddi16sp-01", "2010",
|
||||
"rv32i_m/C/caddi4spn-01", "2010",
|
||||
"rv32i_m/C/cand-01", "4010",
|
||||
"rv32i_m/C/candi-01", "3010",
|
||||
"rv32i_m/C/cbeqz-01", "3010",
|
||||
"rv32i_m/C/cbnez-01", "3010",
|
||||
"rv32i_m/C/cebreak-01", "2050",
|
||||
"rv32i_m/C/cj-01", "3010",
|
||||
"rv32i_m/C/cjal-01", "3010",
|
||||
"rv32i_m/C/cjalr-01", "2010",
|
||||
"rv32i_m/C/cjr-01", "2010",
|
||||
"rv32i_m/C/cli-01", "2010",
|
||||
"rv32i_m/C/clui-01", "2010",
|
||||
"rv32i_m/C/clw-01", "2010",
|
||||
"rv32i_m/C/clwsp-01", "2010",
|
||||
"rv32i_m/C/cmv-01", "2010",
|
||||
"rv32i_m/C/cnop-01", "2010",
|
||||
"rv32i_m/C/cor-01", "4010",
|
||||
"rv32i_m/C/cslli-01", "2010",
|
||||
"rv32i_m/C/csrai-01", "2010",
|
||||
"rv32i_m/C/csrli-01", "2010",
|
||||
"rv32i_m/C/csub-01", "4010",
|
||||
"rv32i_m/C/csw-01", "2010",
|
||||
"rv32i_m/C/cswsp-01", "2010",
|
||||
"rv32i_m/C/cxor-01", "4010"
|
||||
};
|
||||
|
||||
string arch32i[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/I/add-01", "5010",
|
||||
"rv32i_m/I/addi-01", "4010",
|
||||
"rv32i_m/I/and-01", "5010",
|
||||
"rv32i_m/I/andi-01", "4010",
|
||||
"rv32i_m/I/auipc-01", "2010",
|
||||
"rv32i_m/I/beq-01", "39010",
|
||||
"rv32i_m/I/bge-01", "3a010",
|
||||
"rv32i_m/I/bgeu-01", "4a010",
|
||||
"rv32i_m/I/blt-01", "38010",
|
||||
"rv32i_m/I/bltu-01", "4b010",
|
||||
"rv32i_m/I/bne-01", "39010",
|
||||
"rv32i_m/I/fence-01", "2010",
|
||||
"rv32i_m/I/jal-01", "1ad010",
|
||||
"rv32i_m/I/jalr-01", "2010",
|
||||
"rv32i_m/I/lb-align-01", "2010",
|
||||
"rv32i_m/I/lbu-align-01", "2010",
|
||||
"rv32i_m/I/lh-align-01", "2010",
|
||||
"rv32i_m/I/lhu-align-01", "2010",
|
||||
"rv32i_m/I/lui-01", "2010",
|
||||
"rv32i_m/I/lw-align-01", "2010",
|
||||
"rv32i_m/I/or-01", "5010",
|
||||
"rv32i_m/I/ori-01", "4010",
|
||||
"rv32i_m/I/sb-align-01", "2010",
|
||||
"rv32i_m/I/sh-align-01", "2010",
|
||||
"rv32i_m/I/sll-01", "2010",
|
||||
"rv32i_m/I/slli-01", "2010",
|
||||
"rv32i_m/I/slt-01", "5010",
|
||||
"rv32i_m/I/slti-01", "4010",
|
||||
"rv32i_m/I/sltiu-01", "4010",
|
||||
"rv32i_m/I/sltu-01", "5010",
|
||||
"rv32i_m/I/sra-01", "2010",
|
||||
"rv32i_m/I/srai-01", "2010",
|
||||
"rv32i_m/I/srl-01", "2010",
|
||||
"rv32i_m/I/srli-01", "2010",
|
||||
"rv32i_m/I/sub-01", "5010",
|
||||
"rv32i_m/I/sw-align-01", "2010",
|
||||
"rv32i_m/I/xor-01", "5010",
|
||||
"rv32i_m/I/xori-01", "4010"
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user