Ross Thompson 2825074114 Confirmed David's changes to the interrupt code. ... When a timer interrupt occurs it should be routed to the machine interrupt pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is Machine. This is true for all the interrupts. The interrupt should not be masked even though it is delegated to a lower privilege. Since the CPU is currently in machine mode the interrupt must be taken if MIE. Additionally added a new qemu script which pipes together all the parsing and post processing scripts to produce the singular all.txt trace without the massivie intermediate files.		2021-08-22 21:36:31 -05:00
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common	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
imperas-boottim.txt	added sfence to legal instructions, zeroed out rom file to populate for tests	2021-07-23 15:55:08 -04:00
testbench-coremark_bare.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-coremark.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-imperas.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
testbench-linux.sv	Confirmed David's changes to the interrupt code.	2021-08-22 21:36:31 -05:00
testbench-privileged.sv	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00