forked from Github_Repos/cvw
Divide performs 2 steps per cycle
This commit is contained in:
David Harris
parent
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commit
fbe6e41169
@ -1,10 +1,10 @@
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///////////////////////////////////////////
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// intdiv_restoring.sv
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// intdivrestoring.sv
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//
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// Written: David_Harris@hmc.edu 12 September 2021
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// Modified:
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//
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// Purpose: Restoring integer division using a shift register a subtractor
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// Purpose: Restoring integer division using a shift register and subtractor
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//
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// A component of the Wally configurable RISC-V project.
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//
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@ -25,7 +25,7 @@
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`include "wally-config.vh"
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module intdiv_restoring (
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module intdivrestoring (
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input logic clk,
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input logic reset,
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input logic StallM,
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@ -36,9 +36,9 @@ module intdiv_restoring (
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output logic [`XLEN-1:0] Q, REM
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);
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logic [`XLEN-1:0] W, W2, Win, Wshift, Wprime, Wn, Wnn, Wnext, XQ, XQin, XQshift, XQn, XQnn, XQnext, Dsaved, Din, Dabs, D2, Xabs, X2, Xsaved, Xinit;
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logic [`XLEN-1:0] W, W2, Win, Wshift, Wprime, Wn, Wnn, Wnext, XQ, XQin, XQshift, XQn, XQnn, XQnext, Dsaved, Din, Dabs, D2, Xabs, X2, Xsaved, Xinit, DAbsB, W1, XQ1;
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logic qi, qib; // curent quotient bit
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localparam STEPBITS = $clog2(`XLEN);
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localparam STEPBITS = $clog2(`XLEN)-1;
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logic [STEPBITS:0] step;
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logic div0;
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logic negate, init, startd, SignX, SignD, NegW, NegQ;
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@ -53,33 +53,25 @@ module intdiv_restoring (
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mux2 #(`XLEN) xabsmux(X, Xabs, signedDivide & ~div0, X2); // need original X as remainder if doing divide by 0
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flopen #(`XLEN) xsavereg(clk, start, X2, Xsaved);
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mux2 #(`XLEN) xfirstmux(Xsaved, X, start, Xinit);
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// restoring division
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mux2 #(`XLEN) wmux(W, {`XLEN{1'b0}}, init, Win);
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mux2 #(`XLEN) xmux(XQ, Xinit, init, XQin);
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assign {Wshift, XQshift} = {Win[`XLEN-2:0], XQin, qi};
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assign {qib, Wprime} = {1'b0, Wshift} + ~{1'b0, Din} + 1; // subtractor, carry out determines quotient bit
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assign qi = ~qib;
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mux2 #(`XLEN) wrestoremux(Wshift, Wprime, qi, W2);
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assign DAbsB = ~Din;
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intdivrestoringstep step1(Win, XQin, DAbsB, W1, XQ1);
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intdivrestoringstep step2(W1, XQ1, DAbsB, W2, XQshift);
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// conditionally negate outputs at end of signed operation
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// *** move into M stage
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neg #(`XLEN) wneg(W, Wn);
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// mux2 #(`XLEN) wnegmux(W, Wn, NegW, Wnn);
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// mux2 #(`XLEN) wnextmux(W2, Wnn, negate, Wnext);
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mux2 #(`XLEN) wnextmux(W2, Wn, NegW, Wnext);
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mux2 #(`XLEN) wnextmux(W2, Wn, NegW, Wnext); //***
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neg #(`XLEN) qneg(XQ, XQn);
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// mux2 #(`XLEN) qnegmux(XQ, XQn, NegQ, XQnn);
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// mux2 #(`XLEN) qnextmux(XQshift, XQnn, negate, XQnext);
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mux2 #(`XLEN) qnextmux(XQshift, XQn, NegQ, XQnext);
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flopen #(`XLEN) wreg(clk, start | (busy & (~negate | NegW)), Wnext, W);
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flopen #(`XLEN) xreg(clk, start | (busy & (~negate | NegQ)), XQnext, XQ);
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// save D, which comes from SrcAE forwarding mux and could change because register file read is stalled during divide
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// flopen #(`XLEN) dreg(clk, start, D, Dsaved);
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//mux2 #(`XLEN) dmux(Dsaved, D, start, Din);
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// outputs
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// *** sign extension, handling W instructions
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assign div0 = (Din == 0);
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mux2 #(`XLEN) qmux(XQ, {`XLEN{1'b1}}, div0, Q); // Q taken from XQ register, or all 1s when dividing by zero
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mux2 #(`XLEN) remmux(W, Xsaved, div0, REM); // REM taken from W register, or from X when dividing by zero
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@ -124,3 +116,17 @@ module intdiv_restoring (
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endmodule // muldiv
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module intdivrestoringstep(
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input logic [`XLEN-1:0] W, XQ, DAbsB,
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output logic [`XLEN-1:0] WOut, XQOut);
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logic [`XLEN-1:0] WShift, WPrime;
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logic qi, qib;
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assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};
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assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} + 1; // subtractor, carry out determines quotient bit ***replace with add
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assign qi = ~qib;
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mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut);
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endmodule
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// *** clean up internal signals
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@ -47,7 +47,7 @@ module muldiv (
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logic [`XLEN-1:0] MulDivResultE, MulDivResultM;
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logic [`XLEN-1:0] PrelimResultE;
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logic [`XLEN-1:0] QuotE, RemE;
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logic [`XLEN*2-1:0] ProdE;
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logic [`XLEN*2-1:0] ProdE, ProdM;
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logic enable_q;
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//logic [2:0] Funct3E_Q;
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@ -55,19 +55,21 @@ module muldiv (
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logic [`XLEN-1:0] X, D;
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//logic [`XLEN-1:0] Num0, Den0;
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logic gclk;
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// logic gclk;
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logic startDivideE, busy;
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logic signedDivide;
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// Multiplier
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mul mul(.*);
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flopenrc #(`XLEN*2) ProdMReg(clk, reset, FlushM, ~StallM, ProdE, ProdM);
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// Divide
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// *** replace this clock gater
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/*// *** replace this clock gater
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always @(negedge clk) begin
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enable_q <= ~StallM;
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end
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assign gclk = enable_q & clk;
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assign gclk = enable_q & clk; */
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// Handle sign extension for W-type instructions
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if (`XLEN == 64) begin // RV64 has W-type instructions
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@ -80,7 +82,8 @@ module muldiv (
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assign signedDivide = ~Funct3E[0]; // simplified from (Funct3E[2]&~Funct3E[1]&~Funct3E[0]) | (Funct3E[2]&Funct3E[1]&~Funct3E[0]);
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//intdiv #(`XLEN) div (QuotE, RemE, DivDoneE, DivBusyE, div0error, N, D, gclk, reset, startDivideE, signedDivide);
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intdiv_restoring div(.clk, .reset, .StallM, .signedDivide, .start(startDivideE), .X(X), .D(D), .busy(busy), .done(DivDoneE), .Q(QuotE), .REM(RemE));
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// intdivrestoring div(.clk, .reset, .StallM, .signedDivide, .start(startDivideE), .X(X), .D(D), .busy(busy), .done(DivDoneE), .Q(QuotE), .REM(RemE));
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intdivrestoring div(.clk, .reset, .StallM, .signedDivide, .start(startDivideE), .X(X), .D(D), .busy(busy), .done(DivDoneE), .Q(QuotE), .REM(RemE));
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// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
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assign startDivideE = MulDivE & Funct3E[2] & ~busy & ~DivDoneE;
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@ -430,7 +430,7 @@ string tests32f[] = '{
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// tests = {tests64p,tests64i, tests64periph};
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if (`C_SUPPORTED) tests = {tests, tests64ic};
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// else tests = {tests, tests64iNOc};
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if (`M_SUPPORTED) tests = {tests, tests64m};
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if (`M_SUPPORTED) tests = {tests64m, tests};
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/* if (`F_SUPPORTED) tests = {tests64f, tests};
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if (`D_SUPPORTED) tests = {tests64d, tests};
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if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
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@ -449,7 +449,7 @@ string tests32f[] = '{
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tests = {tests32priv, tests32i};
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//tests = {tests32i, tests32priv};
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if (`C_SUPPORTED) tests = {tests, tests32ic};
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if (`M_SUPPORTED) tests = {tests, tests32m};
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if (`M_SUPPORTED) tests = {tests32m, tests};
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//if (`C_SUPPORTED) tests = {tests32ic, tests};
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//if (`M_SUPPORTED) tests = {tests32m, tests};
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/* tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment
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