Added either the sdModel or constant driver for the SDC ports in all test benches.

wally-pipelined/testbench/testbench-arch.sv

@@ -467,6 +467,12 @@ string tests32f[] = '{
 
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
+  logic SDCCLK;
+  tri1 SDCCmd;
+  tri1 [3:0] SDCDat;
+
+  assign SDCmd = 1'bz;
+  assign SDCDat = 4'bz;
 
   // instantiate device to be tested
   assign GPIOPinsIn = 0;

wally-pipelined/testbench/testbench-coremark.sv

@@ -52,6 +52,12 @@ module testbench();
   string signame, memfilename;
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
+  logic SDCCLK;
+  tri1 SDCCmd;
+  tri1 [3:0] SDCDat;
+
+  assign SDCmd = 1'bz;
+  assign SDCDat = 4'bz;
   // instantiate device to be tested
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;

wally-pipelined/testbench/testbench-coremark_bare.sv

@@ -52,6 +52,14 @@ module testbench();
   string signame, memfilename;
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
+  logic SDCCLK;
+  tri1 SDCCmd;
+  tri1 [3:0] SDCDat;
+
+  assign SDCmd = 1'bz;
+  assign SDCDat = 4'bz;
+  
+
   // instantiate device to be tested
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;

wally-pipelined/testbench/testbench-fpga.sv

@@ -569,6 +569,15 @@ string tests32f[] = '{
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
 
+  logic SDCCLK;
+  tri1 SDCCmd;
+  tri1 [3:0] SDCDat;
+
+  sdModel sdcard
+    (.sdClk(SDCCLK),
+    .cmd(SDCCmd), 
+    .dat(SDCDat));
+
   // instantiate device to be tested
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;

wally-pipelined/testbench/testbench-imperas.sv

@@ -588,10 +588,14 @@ string tests32f[] = '{
 
   // SD card model
 
+  assign SDCmd = 1'bz;
+  assign SDCDat = 4'bz;
+/* -----\/----- EXCLUDED -----\/-----
   sdModel sdcard
     (.sdClk(SDCCLK),
     .cmd(SDCCmd), 
     .dat(SDCDat));
+ -----/\----- EXCLUDED -----/\----- */
   
 
   // initialize tests

wally-pipelined/testbench/testbench-linux.sv

@@ -55,6 +55,14 @@ module testbench();
   logic [31:0]      GPIOPinsIn;
   logic [31:0]      GPIOPinsOut, GPIOPinsEn;
   logic             UARTSin, UARTSout;
+
+  logic SDCCLK;
+  tri1 SDCCmd;
+  tri1 [3:0] SDCDat;
+
+  assign SDCmd = 1'bz;
+  assign SDCDat = 4'bz;
+  
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;