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480 Commits

Author SHA1 Message Date
Kevin Kim
288c7ad48c updated license header 2023-03-06 05:41:53 -08:00
Kevin Kim
cec1e89c78 bug fix 2023-03-05 15:20:48 -08:00
Kevin Kim
19beed7866 extend unit structural mux 2023-03-05 15:09:02 -08:00
Kevin Kim
7531bf1fd6 zbb result select mux structural 2023-03-05 14:57:30 -08:00
Kevin Kim
3656d42ac0 zbc input mux structural 2023-03-05 14:26:31 -08:00
Kevin Kim
869e812aa8 revA signals to cnt, zbb 2023-03-05 14:26:24 -08:00
Kevin Kim
0e6ea0ee60 ALU changes 
- added PreShiftAmt signal for shadd
- condinvB now muxes from B instead of mask
 2023-03-05 14:06:24 -08:00
Kevin Kim
3d5ee8d964 bug in bctrl 
- deleted the min/minu decoding for some reason.
 2023-03-04 23:56:33 -08:00
Kevin Kim
6ead150cb1 BSelect from OH encoding to Binary 2023-03-04 23:19:31 -08:00
Kevin Kim
4b1ee5a196 alu pre-shift 
-changed ALU pre shift logic to use a 2 bit shifter instead of mux
 2023-03-04 23:07:06 -08:00
Kevin Kim
b0f152de28 added python script 
-I've been using this python script to make quick changes to the bitmanip controller
 2023-03-04 22:54:32 -08:00
Kevin Kim
499c3c5c30 Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip 2023-03-04 22:44:09 -08:00
Kevin Kim
6295178073 removed rotate signal in datapath and instead packed into the new BALUControl Signal 
- BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU
 2023-03-04 22:44:03 -08:00
Kip Macsai-Goren
0ba1a59a70 added reset values to stime and stimecmp registers 2023-03-04 15:06:15 -08:00
Kip Macsai-Goren
e76e7120c0 Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-04 14:43:12 -08:00
Kevin Kim
b6dd855395 zbc result mux is now structural 2023-03-04 09:22:21 -08:00
Kevin Kim
6e52113208 Rotate signal now gets generated in bmu ctrl 2023-03-03 22:57:49 -08:00
Kevin Kim
18ab538a5e license comments 2023-03-03 21:52:34 -08:00
Kevin Kim
efce306aab removed redundant signals in controller 2023-03-03 21:52:25 -08:00
Kevin Kim
448e950eba b controller generates comparison signed flag and controller branch signed logic updated accordingly 2023-03-03 17:12:29 -08:00
Ross Thompson
dea5aae01e
Merge pull request #126 from davidharrishmc/dev 
ImperasDV setup
 2023-03-03 18:01:32 -06:00
David Harris
39c871ee0c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-03 15:54:42 -08:00
Kevin Kim
0bb75132c6 sltD signal debug. Passes regression 2023-03-03 12:44:33 -08:00
Kevin Kim
d24f74dc4b sltD logic optimize 2023-03-03 12:35:40 -08:00
Kevin Kim
66b15b9163 Merge branch 'bctrlmigrate' of https://github.com/kipmacsaigoren/cvw into bctrlmigrate 2023-03-03 09:54:08 -08:00
Kevin Kim
0dee48fa5c
Merge branch 'openhwgroup:main' into bctrlmigrate 2023-03-03 09:53:59 -08:00
Kevin Kim
77c9114bcc removed outdated b-signals in controller 2023-03-03 08:45:42 -08:00
Kevin Kim
2b9a6aba91 comments to bctrl 2023-03-03 08:41:47 -08:00
Kevin Kim
11f165d1bb migrated B-subarith logic into b controller 2023-03-03 08:40:29 -08:00
Kevin Kim
b5a5f364e1 began subarith configurability optimization in controller 2023-03-03 08:27:11 -08:00
Ross Thompson
7dd8fa16c1 Renamed BTB misprediction to BTA. 2023-03-03 00:18:34 -06:00
Ross Thompson
bdab2c8506 Added divide cycle counter. 2023-03-02 23:59:52 -06:00
Ross Thompson
4b501f6e03 Added the i and d cache cycle counters. 2023-03-02 23:54:56 -06:00
Ross Thompson
b19d51b6a2 Added fence counter. 2023-03-02 23:29:20 -06:00
Ross Thompson
3dbfa96aef Added csr write counter, sfence vma counter, interrupt counter, and exception counter. 2023-03-02 23:21:29 -06:00
Ross Thompson
cf4d8e6bd0 Added store stall to performance counters. 2023-03-02 23:10:54 -06:00
Ross Thompson
e257ec96ac Reordered performance counters and added space for new ones. 2023-03-02 23:04:31 -06:00
David Harris
d51d93a3a8 Refactored Floating point division special case detection to avoid spurious trigger on Y for sqrt) 2023-03-02 20:00:47 -08:00
Kevin Kim
f4b8968e12 bug fix, more elegant logic changes in controller 2023-03-02 16:00:56 -08:00
Kevin Kim
2a0c59d5a7 formatting 2023-03-02 15:28:43 -08:00
Kevin Kim
d0c486df54 removed main instruction decoder dependence on bmu controller 2023-03-02 15:28:33 -08:00
Kevin Kim
11a977ffe3 added bitmanip illegal instruction signal 2023-03-02 15:09:55 -08:00
Kevin Kim
b52208b539 zbc comments 2023-03-02 13:52:00 -08:00
Kevin Kim
2d7d143f6d formatted bmu decoder 2023-03-02 13:45:15 -08:00
Kevin Kim
1b222f91be moved ALUControlD into configurable block 2023-03-02 12:17:03 -08:00
Kevin Kim
1e1ecaafb1 moved SubArith and RegWriteE into configurable block 2023-03-02 12:15:57 -08:00
Kevin Kim
7dd4a2e975 added BRegWriteE signal 2023-03-02 12:15:22 -08:00
Kevin Kim
d40f3b2a1c rename shifternew to shifter 2023-03-02 11:45:32 -08:00
Kevin Kim
905373d53b zbc input select mux optimize 2023-03-02 11:43:05 -08:00
Kevin Kim
2bfbf051a5 zbc select mux optimization 2023-03-02 11:40:29 -08:00
Kevin Kim
44d40afca8 fixed controller lint, changed byte unit mux select name and input width 2023-03-02 11:36:12 -08:00
Kevin Kim
96995c5593 removed redundant zbs 2023-03-02 11:22:09 -08:00
Ross Thompson
3d1ffac7d7 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
David Harris
c761fb1054 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-01 11:18:05 -08:00
David Harris
e78591093e Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA 2023-03-01 11:18:00 -08:00
Ross Thompson
a61f8bc4cf Set bp to use instruction class prediction by default. 2023-03-01 11:52:42 -06:00
Ross Thompson
e8744684cd Branch predictor cleanup. 
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
 2023-03-01 11:24:24 -06:00
Ross Thompson
08a1153ae9 More btb cleanup. 2023-03-01 10:47:00 -06:00
Ross Thompson
dd2433f7ff Minor fix to btb. 2023-03-01 10:45:40 -06:00
Ross Thompson
2773048bd4 Name cleanup. 2023-02-28 17:48:58 -06:00
Kip Macsai-Goren
9e52ede0cd Merge remote-tracking branch 'upstream/main' into bit-manip 2023-02-28 14:41:51 -08:00
Kip Macsai-Goren
2cab4a2f0a Merge remote-tracking branch 'origin' into bit-manip 2023-02-28 14:39:57 -08:00
Ross Thompson
87013ccaf0 Found the performance bug with the branch predictor btb power saving update. 2023-02-28 15:57:34 -06:00
Ross Thompson
8af61c0cc0 Name changes to reflect diagrams. 2023-02-28 15:37:25 -06:00
Ross Thompson
a823d8d021 Undid the btb update as it reduces performance. 2023-02-28 15:21:56 -06:00
Kevin Kim
036cad71c6 bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG] 2023-02-28 12:09:35 -08:00
Kevin Kim
6835a635cc added BRegWrite, BW64, BALUOp signals to bctrl and controller 
-TODO: Main decode in bmuctrl must assert these 3 signals
 2023-02-28 11:54:10 -08:00
Kevin Kim
82059fba67 changed shifter source select signal name 2023-02-28 11:41:40 -08:00
Kevin Kim
30ef1ac9e3 rename result back to ALUResult in ALU 2023-02-28 07:27:34 -08:00
Ross Thompson
3261f31e88 This icpred and btb changes are causing a performance issue. 2023-02-27 20:00:50 -06:00
Ross Thompson
69e8358639 Modified the BTB to save power by not updating when the prediction is unchanged. 2023-02-27 17:37:29 -06:00
Ross Thompson
44361f0a34 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-27 09:48:03 -06:00
David Harris
5c8fee127b Added support for ZMMUL 2023-02-27 07:29:53 -08:00
Ross Thompson
a81cc883e9 Signal name changes. 2023-02-27 00:39:19 -06:00
David Harris
0d3d499940 hptw typo fix 2023-02-26 19:38:34 -08:00
Ross Thompson
447f6b1443 Branch predictor cleanup. 2023-02-26 21:28:36 -06:00
David Harris
907fbfec38 Simplified Access fault logic in HPTW 2023-02-26 18:50:37 -08:00
David Harris
d3f5708ded StoreAmo faults are generated instead of load faults on AMO operations 2023-02-26 18:35:10 -08:00
Ross Thompson
3804626166 Create module for instruction class prediction and decoding. 2023-02-26 20:20:30 -06:00
Ross Thompson
86f611577f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-26 19:58:24 -06:00
David Harris
d2fd34efe6 Renamed DAPageFault to UpdateDA 2023-02-26 17:51:45 -08:00
David Harris
246deeda82 renamed UpperBitsUnequalPageFault to UpperBitsUnequal 2023-02-26 17:32:34 -08:00
David Harris
099267ffce moved tlb to subdirectory 2023-02-26 17:31:03 -08:00
David Harris
a9e884acc8 Moved TLB into subdirectory of MMU 2023-02-26 17:28:05 -08:00
Ross Thompson
bb276da6eb Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-26 12:06:06 -06:00
David Harris
2ad62ea31f Removed unneeded TLBFlush from TLBMiss 2023-02-26 10:04:16 -08:00
David Harris
2203c05724 Access faults are geted by ~TLBMiss rather than ~(Translate & ~TLBHit) 2023-02-26 09:58:34 -08:00
David Harris
4579a9d0c2 Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED 2023-02-26 09:38:32 -08:00
David Harris
e3e5100f8d Renamed DAPageFault to HPTWDAPageFault in hptw to avoid name conflict with DAPageFault from tlbcontrol 2023-02-26 07:12:43 -08:00
David Harris
d50658addf Fixed missing assign when SSTC is not supported 2023-02-26 07:12:13 -08:00
David Harris
27acb90217 Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0 2023-02-26 06:30:43 -08:00
Ross Thompson
7500bb75c6 PHT was enabled using the wrong ~flush and ~stall. 2023-02-24 22:57:32 -06:00
Ross Thompson
63b9f9ca3d gshare cleanup. 2023-02-24 22:55:51 -06:00
Ross Thompson
ed7ab402ad More signal renames. 2023-02-24 19:56:55 -06:00
Ross Thompson
e549bec060 Renamed signals to match new figures. 2023-02-24 19:51:47 -06:00
Kevin Kim
c7050ada78 removed old shifter 2023-02-24 17:33:47 -08:00
Ross Thompson
6ff524d843 Renamed signals to match figure 10.18. 2023-02-24 19:22:14 -06:00
Kevin Kim
b3180d7307 removed now-redundant zero-extend mux in alu 2023-02-24 17:14:12 -08:00
Kevin Kim
0fe1d3b9f3 took sign extension out of shifter 2023-02-24 17:09:56 -08:00
Ross Thompson
ea71fd09f5 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-24 18:50:35 -06:00
Ross Thompson
4058a49985 Possible fix to btb performance issue. 2023-02-24 18:36:41 -06:00
Ross Thompson
5c52827f51 Cleanup. 2023-02-24 18:20:42 -06:00
Ross Thompson
d030d323fd Completed critical path gshare fix. 2023-02-24 18:02:00 -06:00
Ross Thompson
c2021927ce Prep to fix gshare critical path. 2023-02-24 17:54:48 -06:00
Ross Thompson
4ffaa75c2a Modified btb forwarding logic to reduce critical path. 2023-02-24 17:47:43 -06:00
Kevin Kim
a856c5de96 optimized mux to shifter, passes rv32/64i 2023-02-24 12:09:34 -08:00
Kip Macsai-Goren
1ad1c4735d Merge remote-tracking branch 'upstream/main' into bit-manip 2023-02-24 09:28:24 -08:00
David Harris
60752fe51c Fixed special cases of address decoder and documented better 2023-02-24 07:52:46 -08:00
Kevin Kim
f0cf7c2c6a small optimization to condzext select 2023-02-23 21:57:28 -08:00
Ross Thompson
6e8791a0a5 Major cleanup of bp. 2023-02-23 16:19:03 -06:00
Ross Thompson
d880720b7e Partial replacement of InstrClassX with {JalX, RetX, JumpX, and BranchX}. 2023-02-23 15:55:34 -06:00
Kip Macsai-Goren
003ad0618d Merge remote-tracking branch 'upstream/main' into main 2023-02-23 13:33:45 -08:00
Ross Thompson
500764f97b Branch predictor cleanup. 2023-02-23 15:15:14 -06:00
Ross Thompson
70f7f59332 Moved more branch predictor logic into the performance counter block. 2023-02-23 15:14:56 -06:00
Ross Thompson
195343c84f Added if generate around bp logic only used with performance counters. 2023-02-23 14:39:31 -06:00
Ross Thompson
ed91fc5ce3 Renamed PCPredX to BTAX. 2023-02-23 14:33:32 -06:00
Kip Macsai-Goren
f8f89e692e Fixed lint errors on zero and pop count. All of regression passes 2023-02-22 20:25:51 -08:00
Kip Macsai-Goren
82611ba889 Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
21eaa0b989 Merge remote-tracking branch 'upstream/main' into main 2023-02-22 15:47:54 -08:00
Ross Thompson
1af7b8051e Fixed bug in basic gshare. 2023-02-22 12:54:46 -06:00
Ross Thompson
fd5b940839 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-22 09:11:57 -06:00
Ross Thompson
5ecbc830cf Oups. Turns out dc_shell does not like string parameters. 
Switched gshare to use an integer parameter to select between gshare and global.
 2023-02-22 09:11:46 -06:00
Kip Macsai-Goren
66833f15f2 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
Kevin Kim
bb252acfbe added individual zb tests in tests.vh and testbench 
- also minor alu/controller configurability changes
 2023-02-21 11:52:05 -08:00
David Harris
bc4410e686 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-21 09:58:18 -08:00
David Harris
8df7768d32 Fixed Issue #65 fmv sign selection. Sign needs to come from most significant bit of raw X source without doing NaN Box fixes first. 2023-02-21 09:57:57 -08:00
David Harris
0b9fd8a4b3 Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well. 2023-02-21 09:32:17 -08:00
Ross Thompson
fd5c12431e Fixed typo in the global branch predictor. 2023-02-20 18:48:02 -06:00
Ross Thompson
d2e06d9ef0 Cleanup branch predictor files. 2023-02-20 18:45:45 -06:00
Ross Thompson
a14c71bd95 Renamed branch predictors and consolidated global and gshare predictors. 2023-02-20 18:42:37 -06:00
Ross Thompson
68e39eeb66 Fixed another bug in the btb. 2023-02-20 17:54:22 -06:00
Ross Thompson
5187c78184 Fixed forwarding bug in the BTB. 2023-02-20 17:03:45 -06:00
Ross Thompson
d887124837 Found a bug where the d and i cache misses were not recorded in the performance counters. 2023-02-20 16:00:29 -06:00
Ross Thompson
1982c66b72 Simiplified BTB. 2023-02-20 15:39:42 -06:00
David Harris
bdcd867c11 Removed test code that broke LSU 2023-02-20 12:42:46 -08:00
David Harris
c6c21463d9 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-20 11:28:15 -08:00
David Harris
081a817925
Merge pull request #98 from ross144/main 
New gshare implementation
 2023-02-20 11:27:47 -08:00
David Harris
023ba68088 Extraction script updates to match new reports names 2023-02-20 10:16:45 -08:00
David Harris
df9950483e Removed unused and incomplete ROM macro instantations 2023-02-20 05:59:57 -08:00
David Harris
a59526fc8e Fixed IROM size parameters 2023-02-20 05:32:43 -08:00
David Harris
1d3b41e0fb New expression for BTB_SIZE to avoid error during sky90 synthesis 2023-02-20 04:02:00 -08:00
Ross Thompson
2d417c33a4 Simplified BTB by removing the valid bit. the instruction class provides the equivalent information. 2023-02-19 23:53:20 -06:00
Ross Thompson
0d79c0cebe Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-19 22:54:27 -06:00
Ross Thompson
b32093b33b Simplified branch predictor. 2023-02-19 22:49:48 -06:00
David Harris
0ac9c9e62a Added BTB_SIZE parameter independent of BPRED_SIIZE 2023-02-19 20:13:50 -08:00
David Harris
5b197f4f9d Parameterized btb to depend on BPRED_SIZE 2023-02-19 19:59:07 -08:00
Kip Macsai-Goren
8d0a600b96 Merge remote-tracking branch 'upstream/main' into main 2023-02-19 16:37:18 -08:00
David Harris
06872e3822 Adjusted DTIM to always be 512B independent of XLEN 2023-02-19 16:14:38 -08:00
David Harris
5b8d1e4134 PMP checker size check to avoid spurious warnings 2023-02-19 16:08:23 -08:00
David Harris
ac21bed64d Moved conditional instantiation outside pmpchecker 2023-02-19 15:31:00 -08:00
David Harris
7d031fcae0 Disabled W64M register for RV32 2023-02-19 07:03:31 -08:00
David Harris
6d405ad69b Fixed RAM instantiations 2023-02-19 06:31:41 -08:00
Ross Thompson
9ee48637dc Possibly much better branch predictor implemention. 
The complexity is significantly reduced.
 2023-02-19 00:17:37 -06:00
Kevin Kim
2069d92f9e B DONE (for now) 
- datapath passes along comparator flag to alu
-  controllers and zbb handle min/max instructions
 2023-02-18 22:12:55 -08:00
Ross Thompson
d44cb1febb Minor fix. 2023-02-18 23:55:46 -06:00
Kevin Kim
888f4318bc controlleres and zbb handle byte instructions 2023-02-18 21:06:55 -08:00
Kevin Kim
27581f8d28 alu and controllers handle andn, orn, xnor 2023-02-18 20:57:07 -08:00
Kevin Kim
ba968ed95e added logic to handle sign/zero extend instructions 2023-02-18 20:32:40 -08:00
Kevin Kim
5c563bef43 fixed ctlzw bug in count unit 2023-02-18 20:12:30 -08:00
Kevin Kim
6d60268240 zbb handles count instructions 2023-02-18 20:12:17 -08:00
Kevin Kim
9760f0ccfd fixed bmuctrl decode bug 2023-02-18 20:11:50 -08:00
Kevin Kim
84ddb6fb54 updated comments in bmuctrl 2023-02-18 19:57:10 -08:00
Kevin Kim
bec2905ee5 rotate instructions now handled in ZBB unit 2023-02-18 19:56:54 -08:00
Kevin Kim
e47cc222a6 removed redundant decode logic in bmuctrl 2023-02-18 19:50:36 -08:00
Kevin Kim
9203b0cc2f began ZBB integration into ieu 2023-02-18 19:44:14 -08:00
Kevin Kim
7780cbd47a bmuctrl handles roriw 2023-02-18 16:26:16 -08:00
Kip Macsai-Goren
883a6ca005 merge upstream synth changes 2023-02-18 14:35:19 -08:00
David Harris
0eda753dc4 Removed unused PredInstrClassE register from bpred 2023-02-18 05:59:25 -08:00
David Harris
0f4226a950 Removed unused weq0M register fron fdivsqrtpostproc 2023-02-18 05:57:39 -08:00
David Harris
66e5c60fb4 Fixed issue #57 of sign selection for improperly NaN-boxed number 2023-02-18 05:34:40 -08:00
David Harris
5986931fdc Fixed unpacking of illegal NaN box. Fixed issue #56 of sign injection NaN 2023-02-18 05:25:38 -08:00
Kevin Kim
92c0d3a4ed configured shifter in alu 2023-02-17 21:58:49 -08:00
Kevin Kim
182b27dfc8 shifter bug fix 
- roli not passing unless I keep the MSB (instead of inverting) of truncated offset
 2023-02-17 21:58:26 -08:00
Kevin Kim
c353378da8 controller supports some rotates 2023-02-17 21:57:34 -08:00
Kevin Kim
4a52b57002 bmuctrl supports some rotates 2023-02-17 21:57:19 -08:00
David Harris
dc19f8a8ec Created PostBox signal to NaN-box malformed NaNs of excess length. Fixes Issue #55 2023-02-17 20:51:43 -08:00
Kevin Kim
50ec6baa07 added zero extend, pre-shift mux to ALU 2023-02-17 20:15:12 -08:00
Kevin Kim
e2d90a9422 more elegant ZBA logic in controller 2023-02-17 20:14:47 -08:00
Kevin Kim
cd92d6e5d1 bmuctrl handles .uw instructions 2023-02-17 20:14:13 -08:00
David Harris
a194740562 Fixed RAM bugs and refactored with read taking place after clock edge rather than before. 2023-02-17 19:14:38 -08:00
Kevin Kim
750882455f controller supports ZBA instructions 2023-02-17 16:44:16 -08:00
Kevin Kim
fcae58fcc7 removed Funct7 in Execute Stage 2023-02-17 16:12:09 -08:00
David Harris
9275bfb839 Memory synthesis updates 2023-02-17 15:33:49 -08:00
David Harris
2060683770 Continue fixing memory macros for synthesis 2023-02-17 15:15:37 -08:00
Ross Thompson
0cacfbd322 Renamed globalhistory predictor. 2023-02-17 16:08:34 -06:00
Ross Thompson
2f1bebfd57 Fixed global history predictor. 2023-02-17 16:05:48 -06:00
Ross Thompson
a95be0b567 More updates. 2023-02-17 15:53:49 -06:00
Ross Thompson
df4a27a2e3 Updated global history predictor. 2023-02-17 15:53:15 -06:00
David Harris
3523318acb Synthesis with memories 2023-02-17 13:51:05 -08:00
Ross Thompson
0d271130b9 Fixed a branch predictor performance issue. 2023-02-17 15:37:03 -06:00
Kevin Kim
9bf11471aa bmuctrl checks for illegal zbs-style instructions 2023-02-17 12:54:08 -08:00
Kevin Kim
0bab3bec3d bctrl bug fix 
- bctrl decodes shift immediate instructions properly
 2023-02-17 11:16:29 -08:00
Kevin Kim
bb79b57cc1 alu bug fix 
- condmaskb piped in correctly instead of b
 2023-02-17 11:02:07 -08:00
Kevin Kim
ee3a520a1f alu looks at BSelect, added BSelect one hot signal 2023-02-17 09:51:49 -08:00
Ross Thompson
5d5e4580d4 Merge branch 'main' of github.com:ross144/cvw 2023-02-17 10:58:16 -06:00
Ross Thompson
a325adf1be Fixed bug with branch predictor. 2023-02-17 10:57:50 -06:00
Kevin Kim
890c54bc0b added alu changes to previous commit 2023-02-17 08:22:13 -08:00
Kevin Kim
ec2421ead4 added BSelect Signal 
- BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
 2023-02-17 08:21:55 -08:00
Kevin Kim
81cb00aaee comments 2023-02-17 07:53:14 -08:00
Kevin Kim
505f3bf42f comments 2023-02-17 07:52:54 -08:00
Kevin Kim
256d362e0d comment formatting 2023-02-17 07:51:28 -08:00
Kevin Kim
9ab8183e80 alu handles ALU select instead of funct3 2023-02-17 07:51:10 -08:00
Kevin Kim
9128ac5409 added BMU controll 2023-02-17 07:50:59 -08:00
Kevin Kim
25c0811d3d Added ALUSelect signal into datapath, ieu, controller 2023-02-17 07:50:45 -08:00
David Harris
c3cc2f98d6 Reverted lab3 changes in dev branch 2023-02-16 18:10:05 -08:00
David Harris
5fef9de80e Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev 2023-02-16 17:57:51 -08:00
David Harris
532abb5b95
Update datapath.sv 2023-02-16 17:53:31 -08:00
David Harris
6527257305
Update controller.sv 2023-02-16 17:52:44 -08:00
David Harris
685d3ff568
Update alu.sv 2023-02-16 17:52:25 -08:00
Ross Thompson
27f6552315 keep this commit off of cvw. 2023-02-16 11:05:24 -06:00
David Harris
d83c61cafc Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass. 2023-02-16 07:37:12 -08:00
Kevin Kim
465aad372a added comments to zbc units 2023-02-15 17:42:32 -08:00
Kevin Kim
aad4d13603 zbc configurability and select mux 2023-02-15 17:39:37 -08:00
Kevin Kim
068ddc3e0d controller forwards funct7 
- started the bmu controll register
 2023-02-15 17:38:12 -08:00
Kevin Kim
6ac54a180e zbc and carry-less multiply work properly 2023-02-15 17:37:09 -08:00
James Stine
744991bd5a Update if-then-else for ram items 2023-02-15 18:12:12 -06:00
Kevin Kim
cf8392cbd8 continued ZBC integration into ALU 2023-02-15 09:35:07 -08:00
Ross Thompson
69472b8145 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-15 11:29:39 -06:00
Kevin Kim
5426dd6184 added ALUResult Signal 2023-02-15 09:13:10 -08:00
Kevin Kim
9cec59ea2c controller passes funct7 from decode to execute 2023-02-14 16:06:10 -08:00
Kevin Kim
70f2dd701c git 2023-02-14 16:03:26 -08:00
Kevin Kim
9728e00dfd Merge branch 'tmp' into main 2023-02-14 13:12:57 -08:00
Kevin Kim
85c2ed8d34 removed unncessary stuff 2023-02-14 13:07:03 -08:00
Kevin Kim
8e371864e4 reverted back to I tests working 2023-02-14 13:06:31 -08:00
Kevin Kim
fd46e0080c added ALU result select mux for B instructions 2023-02-13 17:38:00 -08:00
Kevin Kim
84ca2cab9c controller handles bclr 2023-02-13 16:57:05 -08:00
Ross Thompson
094b307724 Merge branch 'main' of github.com:ross144/cvw 2023-02-13 18:54:07 -06:00
Ross Thompson
9c9acc0055 Updated gshare (no speculation) to have better performance. 2023-02-13 18:52:52 -06:00
Kevin Kim
29abec2409 Shadd instructions pass tests 2023-02-13 16:36:17 -08:00
Ross Thompson
33d2bf84f8 More fixeds to global history. 2023-02-13 18:08:51 -06:00
Ross Thompson
a579bbcdd1 Fixed global history predictor. 2023-02-13 18:08:13 -06:00
Ross Thompson
bbc6095260 Updated global history predictor. 2023-02-13 18:07:32 -06:00
Ross Thompson
9f25b53b36 Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now. 2023-02-13 17:57:05 -06:00
Ross Thompson
b298a8afc5 Created copy of gshare. I think there may be a simpler implementation. 2023-02-13 17:29:51 -06:00
Ross Thompson
a80dbd3aec Further branch predictor improvements. 2023-02-13 17:23:56 -06:00
Ross Thompson
717cba270c Partial improvement. 2023-02-13 17:10:24 -06:00
Ross Thompson
f4af38a004 Hacked commit. Fixes the gshare bugs introduced last week. 
Need to recover the good changes in the next commit.
 2023-02-13 16:14:17 -06:00
Kevin Kim
27223a05e2 ALU lint fixes 2023-02-13 14:01:51 -08:00
Kevin Kim
29d03dbfc7 ALU configurability changes 
-stuff that was ZBA supported was in ZBB so I changed that
 2023-02-13 14:00:06 -08:00
Kevin Kim
12911440d0 edited controller so that add.uw passes tests 2023-02-13 13:49:46 -08:00
Kevin Kim
7eb41058c7 alu add.uw needs w64 to be false 2023-02-13 13:49:35 -08:00
Ross Thompson
1d74663f42 Partial fix for gshare bugs from the last two weeks. 2023-02-13 11:57:25 -06:00
Ross Thompson
58749a8c57 Removed another bit from btb class. 2023-02-12 11:33:43 -06:00
Kevin Kim
31787c456b simulation runs-- clmul doesn't pass lint with xor tree 2023-02-11 21:22:33 -08:00
Kevin Kim
5f08322e99 lint fixes 2023-02-11 21:13:10 -08:00
Kevin Kim
6a7fe6352e zbb, zbs, cnt lint fixes 2023-02-11 20:41:52 -08:00
Kevin Kim
61b46e0639 fixed byte unit lints 2023-02-11 20:25:34 -08:00
Kevin Kim
fb99bdab82 fixed lints in cnt 2023-02-11 20:22:42 -08:00
Kevin Kim
c59dfc1e30
fixed typo in LZC 2023-02-11 19:59:03 -08:00
Kevin Kim
38087be3b7 popcnt passes lint 2023-02-11 19:19:38 -08:00