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898 Commits

Author SHA1 Message Date
Ross Thompson
b70baed214 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
e2cf941a23 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
d91fd44ea5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
dbe4b4bafa added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
bcb4ebf888 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
c4f1a0362b Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
92a2ad02db Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
39a3bf5cdc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
b832a21b73 ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
slmnemo
e3a7e3e2f3 changes suggested by ben, hopefully fixing buildroot (which is now not running) 2022-05-20 18:42:38 -07:00
Katherine Parry
5d34db85b2 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
0afac6904e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 18:31:56 -07:00
slmnemo
af0300c3d7 added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
slmnemo
11e703c8c0 fixed lint autofailing due to no log being produced in regression-wally 2022-05-19 18:30:59 -07:00
slmnemo
79c28d34dc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 17:51:45 -07:00
slmnemo
e4024eb503 Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace 2022-05-19 17:51:26 -07:00
slmnemo
e33ca59d46 Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py 2022-05-19 17:50:48 -07:00
slmnemo
8b27c1884e Fixed buildroot by adding a second . 2022-05-19 17:49:32 -07:00
slmnemo
89c7438424 parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do 2022-05-19 16:21:38 -07:00
Katherine Parry
ab1f088672 fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
6f2d8c24ad Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
bab7335bee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
d34f4a7c3c updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
738bbf6479 Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
c96f07ad75 added instructions to slack notifier 2022-05-18 16:50:31 -07:00
mmasserfrye
84422f3859 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
f8722f04f9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-18 16:10:36 +00:00
mmasserfrye
12c42cd507 adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
b853c4ba47 Updated fpga debugger. 2022-05-17 23:04:01 -05:00
slmnemo
23d6791b22 simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
slmnemo
82e68f2170 Revert "same as last breaking commit, testing if the bisect works to output a breaking commit." 
This reverts commit dcb485ec61.

gottem
 2022-05-17 17:26:33 -07:00
slmnemo
dcb485ec61 same as last breaking commit, testing if the bisect works to output a breaking commit. 2022-05-17 17:22:09 -07:00
slmnemo
b7d036f3d0 Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D." 
This reverts commit f970cc3ea9.

fixed it
 2022-05-17 17:05:11 -07:00
slmnemo
f970cc3ea9 broke it again but this time it doesn't compile due to a missing semicolon on Rs1D. 2022-05-17 17:03:16 -07:00
slmnemo
589bd0ca34 Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression" 
This reverts commit 4908f77cf9.

unbroke wally
 2022-05-17 16:57:29 -07:00
slmnemo
357d77d332 Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"" 
This reverts commit 0e3099743c.

reverted the wrong commit
 2022-05-17 16:57:00 -07:00
slmnemo
0e3099743c Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 
This reverts commit 1c5a3de6d5, reversing
changes made to 1ff47888a7.

undid things
 2022-05-17 16:54:29 -07:00
slmnemo
4908f77cf9 Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression 2022-05-17 16:33:09 -07:00
slmnemo
1c5a3de6d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Added empty directory '/wkdir' to /pipelined/regression to avoid tests failing out of box due to the missing directory
 2022-05-17 20:32:53 +00:00
slmnemo
1ff47888a7 added wkdir in regression so regression runs out of box (assuming the old version of arch tests) 2022-05-17 20:32:38 +00:00
David Harris
a2280dadfd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 15:09:52 +00:00
David Harris
49f25bd03d Restored srt to working without exponent unit 2022-05-17 15:09:48 +00:00
mmasserfrye
2254a8218d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00
mmasserfrye
d34a942eb2 added 8 and 128 bit versions, adjusted alu 2022-05-17 01:11:43 +00:00
slmnemo
e4f0f55530 Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature. 2022-05-17 01:04:13 +00:00
slmnemo
7656e3031c quit 2022-05-17 01:03:09 +00:00
David Harris
8851ddd905 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 00:07:09 +00:00
David Harris
1bcbdcf57d removed exptestgen 2022-05-17 00:06:44 +00:00
David Harris
ea3e7006d9 Cleaned up unpacker changes in srt and lint errors 2022-05-17 00:06:14 +00:00
slmnemo
8c8a7daec2 Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
mmasserfrye
68a70ed8ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
resolved merge conflict
 2022-05-16 15:42:59 +00:00
mmasserfrye
b82520237c tuning modules for ppa 2022-05-16 15:39:15 +00:00
David Harris
48e89485dd Cause simplification 2022-05-12 23:47:21 +00:00
David Harris
9651ced9bb Cause simplification 2022-05-12 23:39:10 +00:00
David Harris
2f283d9654 Cause simplification 2022-05-12 23:37:40 +00:00
David Harris
f5f1870077 Cause simplification 2022-05-12 23:33:35 +00:00
David Harris
5b7cccbc4b Cause simplification 2022-05-12 23:33:22 +00:00
David Harris
581d841653 Cause simplification 2022-05-12 23:29:35 +00:00
David Harris
2a3f545e0c Cause simplification 2022-05-12 23:27:02 +00:00
David Harris
c2b9fc0d8e trap/csr cleanup 2022-05-12 22:26:21 +00:00
David Harris
292d1f33da More trap/csr simplification 2022-05-12 22:06:03 +00:00
David Harris
662fffa830 More trap/csr simplification 2022-05-12 22:04:20 +00:00
David Harris
16b86c199c More trap/csr simplification 2022-05-12 22:00:23 +00:00
David Harris
5f358a37c6 More trap/csr simplification 2022-05-12 21:55:50 +00:00
David Harris
21ac969c7d Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
David Harris
072c464dc1 Simplified MTVAL logic 2022-05-12 21:36:13 +00:00
David Harris
14f9f41d2d Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
David Harris
78448c7053 privileged cleanup 2022-05-12 20:21:33 +00:00
mmasserfrye
31f372e7b3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 20:20:40 +00:00
mmasserfrye
a10b8e47af cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
dd61afb7dc Formatting cleanup 2022-05-12 18:37:47 +00:00
mmasserfrye
01685b982c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 18:08:20 +00:00
mmasserfrye
b089ee26ee renamed madzscript, modified ppa.sv alu and shifter 2022-05-12 18:05:02 +00:00
David Harris
fde8375fbd Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
David Harris
2ceed15bd5 Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
David Harris
1e5d94bbab Moved WFI timeout into privdec 2022-05-12 16:22:39 +00:00
David Harris
39ceb3a550 Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
David Harris
e81e530f68 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
ce24c080d5 More unused signal cleanup 2022-05-12 15:26:08 +00:00
David Harris
5670f77de2 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
4edf9b6355 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
1aa3e65bae Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
e2e63ca9a8 Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
f17501ed8c Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
545d46acb9 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
1e7401daa0 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
999754801c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
6cba6a92ba filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
9999f69922 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
9dd378098f merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
1f761c4e06 PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
552a55d631 ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
David Harris
8166fd772e Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
137b411bea Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
490902a655 Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
bb24aebebd Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
04fd22aeb0 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
4f1b0fdc64 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
1a5bfcf078 Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
a516f89f22 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
412d4656ed Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
7f42ff06d2 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
f436e93fc5 SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
9b7aab122e wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
1a7599ce94 Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
b155effe66 put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
895a4f4832 updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
David Harris
8a43d6099b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
4b91fddc0a Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
3efbd2565a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
20bbe43a23 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
1166c40059 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
bcd8728b3e Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
b4a422f771 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
057524b840 Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
9e50c3440d sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
0df73d203b Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
9e47fca2b7 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
Kip Macsai-Goren
75e90f193e added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
c0b56bfd27 renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c47ec36bc7 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
746fcfde30 set WFI timeout to after 16 bits of counting for all configs 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
aedf0341af added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Skylar Litz
64a537c59b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-27 10:50:19 -07:00
Skylar Litz
f2b6842edb fix AttemptedInstructionCount from ground zero 2022-04-27 10:45:40 -07:00
David Harris
515270a8cf Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
cce0a421be Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9d82232c14 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
4b00531d77 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
74b103fae4 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
Kip Macsai-Goren
33875b20b5 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
Kip Macsai-Goren
2e0f45eab4 removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
01f8bdfafc added new tests to tests.vh, comented out until they pass regression 2022-04-25 18:22:44 +00:00
Kip Macsai-Goren
992cedbc52 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
David Harris
0957b7040d Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
1a8369b02b Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
142636173e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
28e8aa4f97 Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
ffecdda6e6 Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
04b0579b89 Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
bd87af478a Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
9eec1a83a6 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
9c1e398bb5 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
e56b9f18d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
a86274a1e0 Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
1e19cf9f14 Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
25d0f6305a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
8e72ace5ac fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
324d3fcea5 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
b94927d8a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
c57b9e6703 Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
eaa0d44980 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
ced763beb6 Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
121cc627f6 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
6f0085201b replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
a8b3cc8cf9 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
22842816a8 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
61dbf13a69 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
e04febdb57 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
c07b9d1722 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
6504017044 Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
a5d4e39e7d Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
3add26be64 fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
d8b4c985cd Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
6bb4cd1bca Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
5bb521635e Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
331efcedc4 added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Ross Thompson
5a6ad32688 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
b4902a6ff9 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
6769f0cb43 Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
d71940d96d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
55c667b60d Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
f8bdb6db49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69 Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
0932d4df46 Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
c3bca40e05 Added WFI to the testbench instruction name decoder 2022-04-14 17:12:11 +00:00
David Harris
6e16922aae WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
bbracker
0e183be3e5 fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM 2022-04-14 09:23:21 -07:00
bbracker
489ce4269a fix ReadDataM forcing 2022-04-13 15:32:00 -07:00
Ross Thompson
65573f07b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
c697c17b05 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
016e960401 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
3465d8cd32 improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
67ef47b25b whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
6c3d274970 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
2eb2263e94 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
adb4e30c45 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
d087deef65 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010 Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
56bea58a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
fc5eac6820 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
c0c5733a1d upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs 2022-04-08 13:45:27 -07:00
bbracker
23406d0926 small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
Ross Thompson
de868ef3a2 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Ross Thompson
1614996941 Fixed typo in tests.vh 2022-04-07 16:28:28 -05:00
Katherine Parry
74e0db04ac fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
Kip Macsai-Goren
c3a6b88acc updated test signature locations 2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
fbcb0c0bd8 Added missing ZFH macro to new configs 2022-04-06 07:13:51 +00:00
David Harris
7f462a6168 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-05 23:23:47 +00:00
David Harris
23da303ad3 Added bootmem source ccode 2022-04-05 23:22:53 +00:00
Ross Thompson
900939581e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Katherine Parry
c3d07b2c46 generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
91e99f0d34 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
b77201143f Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
38160fe6ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
Ross Thompson
3ebb7f1057 fpga simulation works again. 2022-04-03 17:31:07 -05:00
David Harris
fb95767da0 Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
Ross Thompson
3db60a1cc1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Kip Macsai-Goren
37c755e6ce added RV64IA config to have a config without compressed instructions 2022-04-02 18:24:08 +00:00
Ross Thompson
691f1a6b0d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 17:18:25 -05:00
Ross Thompson
51dfa16f59 Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
Ross Thompson
48c49802b2 Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
301f20052b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
9d26bfe71d expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00
bbracker
e09079d8b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
55df8bc3f7 fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
48c862d536 Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
da93d14050 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
b5cdf035fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
ade4a4cd5e Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
bdb3417656 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
0f7e995055 simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
c7043e4d63 Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
88c5cdc873 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
bf9683f0d2 Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
54001222cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
285fc6fd4d Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
dd3af17b3f Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
3457c6e512 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
69a0f6e00b big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
0a5b500aca Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
9b1f85d353 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
David Harris
08fad856e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:13:42 +00:00
Ross Thompson
e4f4e1bd43 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
f52ab01362 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
997c1b87fe rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
66e9380cfb Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
Kip Macsai-Goren
d031c003ba fixed arch bge test signature output location after update 2022-03-29 20:45:18 +00:00
David Harris
03fa9084bc Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
c4f2c6b110 fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
56a0542405 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00