Ross Thompson
9ec624702d
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Katherine Parry
0c2b7a1132
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
bbracker
751e606fb7
trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug
2021-06-26 08:30:58 -04:00
bbracker
17afd9e5e8
temporarily disable PMP checking for EBU accesses.
2021-06-26 07:19:51 -04:00
bbracker
74833dc68c
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
Ross Thompson
d80ebab941
AMO and LR/SC instructions now working correctly.
...
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Ross Thompson
57a7074800
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341
Working through a combo loop.
2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
5b47da21ba
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
34dbad967d
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
192171826b
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
d7e518991e
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
ac597d78c8
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Katherine Parry
7e3483b283
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
2155a4e485
Revert "fixed forwarding"
...
This reverts commit 86e369df52
2021-06-24 17:39:37 -04:00
Ross Thompson
6bab454b17
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
c02141697d
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
aeeaf6d919
Progress.
2021-06-24 13:05:22 -05:00
bbracker
86e369df52
fixed forwarding
2021-06-24 11:20:21 -04:00
bbracker
2d9c91096b
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
53d545cdfe
regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
bbracker
cee468b21a
whoops meant to remove notifications from busybear, not buildroot
2021-06-24 01:54:46 -04:00
bbracker
13df69abdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
be962cb1ff
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
286b4b5b26
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
8eed89616c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
349f6a9471
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
a514554eeb
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
fc851ca795
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
303f8e2a7f
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
67cf2e1c90
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
353a27f12f
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
7e06a3c04d
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
2c41da0275
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
3e19eba20d
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
bbracker
9b27cd6fb7
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
Ross Thompson
f79e5eaa47
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
3cbe4c9bc2
Improved some names in icache.
2021-06-21 16:40:37 -05:00
David Harris
7930c2ebb4
Commented out 100k tests to improve speed
2021-06-21 01:43:18 -04:00
David Harris
5d6dc82db2
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
1ec90a5e1f
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
d2ec04564b
Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
2021-06-20 22:59:04 -04:00
bbracker
23f479d225
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
bbracker
bf3c2dc089
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 22:29:40 -04:00
bbracker
3000c27acd
linux actually uses FPU now!
2021-06-20 22:29:21 -04:00
Katherine Parry
2b67f25683
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-20 20:24:09 -04:00
bbracker
2643130c41
read from MSTATUS workaround because QEMU has incorrect MSTATUS
2021-06-20 10:11:39 -04:00
bbracker
14ae87ff0a
testbench update b/c QEMU extends 32b CSRs to 64b
2021-06-20 09:24:19 -04:00
bbracker
83a0a37f8e
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
bbracker
dc26f2a6d0
whoops wavedo typo
2021-06-20 05:36:54 -04:00
bbracker
c77aabdc6f
make buildroot ignore SSTATUS because QEMU did not originally log it
2021-06-20 05:31:24 -04:00
bbracker
918ff5093a
MSTATUS workaround
2021-06-20 04:48:09 -04:00
bbracker
069a79fafd
workaround for ignoring MTIME
2021-06-20 02:26:39 -04:00
bbracker
086f031b84
remove lingering busybear stuff from buildroot do files
2021-06-20 00:50:53 -04:00
bbracker
8462f248aa
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 00:40:44 -04:00
bbracker
d62d9a7aac
make buildroot waves only turn on after a user-specified point
2021-06-20 00:39:30 -04:00
Ross Thompson
70c45a5349
Revert "Icache now uses physical lenght bits rather than XLEN."
...
This reverts commit 16266d978a
2021-06-19 08:58:34 -05:00
Ross Thompson
868ddce5f2
Revert "Improved some names in icache."
...
This reverts commit a57c63aa7b
2021-06-19 08:58:32 -05:00
bbracker
a3eafc6e5b
change buildroot config to use relative path for testvectors
2021-06-18 22:28:07 -04:00
bracker
26512348b0
gitignore merge
2021-06-18 21:12:05 -05:00
bracker
34f17b90ea
handle tera usernames more gracefully
2021-06-18 21:11:14 -05:00
bbracker
1781ae9c93
on-Tera solution for sym linking to linux testvectors
2021-06-18 22:01:18 -04:00
bracker
cd7d403f92
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 20:41:01 -05:00
bracker
0addf4a297
script support for copying large files from tera
2021-06-18 20:40:19 -05:00
bbracker
cb949851d9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 17:37:49 -04:00
bbracker
8d242d73b5
fixed PCtext error by using blocking assignments
2021-06-18 17:37:40 -04:00
Ross Thompson
99e3a0db28
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-18 12:24:42 -05:00
Ross Thompson
a57c63aa7b
Improved some names in icache.
2021-06-18 12:22:41 -05:00
Ross Thompson
16266d978a
Icache now uses physical lenght bits rather than XLEN.
2021-06-18 12:02:59 -05:00
David Harris
33312caeb1
Restored wally-busybear testbench now that graphical sim is working
2021-06-18 12:36:25 -04:00
bbracker
03a45aeef1
restore graphical buildroot sim
2021-06-18 11:58:16 -04:00
Abe
a0a4b09c94
Updated directory coremark_bare's wally-config file to define PMP_ENTRIES
2021-06-18 11:46:25 -04:00
bbracker
5095c73dde
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 09:49:37 -04:00
bbracker
4f50dd575d
buildroot added to regression because it passes regression
2021-06-18 09:49:30 -04:00
David Harris
580ac1c4df
Made MemPAdrM and related signals PA_BITS wide
2021-06-18 09:36:22 -04:00
David Harris
de221ff2d0
Changed physical addresses to PA_BITS in size in MMU and TLB
2021-06-18 09:11:31 -04:00
bbracker
c25905ac70
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 08:15:40 -04:00
bbracker
faae30c31c
remove unused testbench-busybear.sv
2021-06-18 08:15:19 -04:00
David Harris
df7e373c69
Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX
2021-06-18 08:13:15 -04:00
David Harris
35c74348a4
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
David Harris
336936cc39
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
David Harris
de3a0c644b
Further cleaning of PMA checker
2021-06-17 22:27:39 -04:00
David Harris
679e507cc6
Added SUPPORTED to each peripheral in each config file
2021-06-17 21:36:32 -04:00
David Harris
54b6a2dcad
added inputs to pmaadrdec
2021-06-17 18:54:39 -04:00
David Harris
da8eb7749f
Started simplifying PMA checker
2021-06-17 16:28:06 -04:00
bbracker
2bee4eabab
added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
2021-06-17 12:09:10 -04:00
bbracker
b65adbea63
enable TIME CSR for 32 bit mode as well
2021-06-17 11:34:16 -04:00
bbracker
5a661a7392
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
bbracker
5b96f7fbd7
making linux waveforms more useful
2021-06-17 08:37:37 -04:00
bbracker
9bc5ddf5f2
PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
2021-06-17 05:19:36 -04:00
bbracker
b459d0cc80
changed parsedCSRs2] to parsedCSRs
2021-06-17 05:18:14 -04:00
bbracker
c4983f4388
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-17 00:50:14 -04:00
bbracker
6625f74a85
still not sure if QEMU workaround is correct, but here is all linux progress so far
2021-06-17 00:50:02 -04:00
bbracker
7b98e7aa2f
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
bbracker
3b9ecc8275
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-16 16:17:53 -04:00
bracker
f99c91553f
chmod +x'd privileged testgen scripts
2021-06-16 10:28:57 -05:00
bbracker
9c883054c7
fixed incorrect expectation fof CLINT spec
2021-06-15 19:24:24 -04:00
bbracker
cd00e04943
Merge remote-tracking branch 'origin/fixPrivTests' into main
2021-06-15 09:57:46 -04:00
Katherine Parry
4177f4f148
Updated FMA
2021-06-14 13:42:53 -04:00
David Harris
c6ff11c22e
disabled Verilator WIDTH warnings in ICCacheCntrl
2021-06-12 19:50:06 -04:00
Ross Thompson
294f01cbd8
fixed the mtime register.
2021-06-11 13:50:13 -05:00
James E. Stine
11c88c15d5
Put repository of fpdivsqrt with RTL-based adder instead of structural implementation
2021-06-11 14:35:22 -04:00
bracker
8794bf1afa
attempt no 1: just change out x28s for x31s
2021-06-11 12:39:28 -05:00
David Harris
49b5fa3994
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
David Harris
e41a87be23
Restored counter events
2021-06-10 11:18:58 -04:00
David Harris
d386929c0e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-10 10:47:55 -04:00
David Harris
802238643a
Removed two cycles of latency from the DTIM
2021-06-10 10:30:24 -04:00
bbracker
f272cd46d8
peripheral lint fixes
2021-06-10 10:19:10 -04:00
bbracker
d4aeb1c387
merge
2021-06-10 10:03:01 -04:00
bbracker
0321d74562
attempt to fix regression by adding PMP_ENTRIES to configs
2021-06-10 09:59:26 -04:00
bbracker
d9022551c2
buildroot progress -- able to mimic GDB output
2021-06-10 09:58:20 -04:00
bbracker
79e798a641
UART improved and added more reg read side effects
2021-06-10 09:53:48 -04:00
David Harris
3e8026dc21
Configurable number of performance counters
2021-06-10 09:41:26 -04:00
David Harris
75870a16d7
Restored PCCorrectE declaration in IFU
2021-06-09 21:09:16 -04:00
David Harris
0ffbd03139
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
David Harris
c7e57aeb1a
removed verilator lint_off WIDTH
2021-06-09 21:01:44 -04:00
David Harris
01d6ca1e2a
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
David Harris
2952550db7
More PMP entries
2021-06-08 15:33:06 -04:00
David Harris
90e5781471
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
a95a7a7b82
working version with new mmu comments, old boottim values
2021-06-08 15:20:25 -04:00
Kip Macsai-Goren
2155cb2e91
merge of reverted main into up to date main
2021-06-08 14:57:43 -04:00
Kip Macsai-Goren
361c71c5e9
reverted to working version with new mmu comments
2021-06-08 14:56:00 -04:00
David Harris
b613f46c2d
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
Kip Macsai-Goren
aab7bd94f7
Merge small mmu changes into main
2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
d6f47d5917
making mmu branch line up with main
2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
e209dbcf50
some cleanup of signals, not done yet
2021-06-08 13:39:32 -04:00
bbracker
cc91c774a6
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
e7e4105931
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
49515245d9
remove redundant decodes, fixed mmu logic ins/outs
2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
1e174a8244
got rid of some underscores in filenames, modules
2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
c96695b1b6
implemented simpler page mixers, cleaned up a bit
2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
b27abc53e8
began updating cam line to reduce muxes, confusion
2021-06-07 17:03:31 -04:00
Kip Macsai-Goren
6a63ad04d2
regression working partially done page mask
2021-06-07 17:02:31 -04:00
David Harris
9efbffdee5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-07 16:14:13 -04:00
David Harris
43a690dc42
Simplified superpage matching
2021-06-07 16:11:28 -04:00
Katherine Parry
0acf665a8b
lint is clean
2021-06-07 14:22:54 -04:00
bbracker
28c6d60150
temporarily removing buildroot from regression until it is regenerated
2021-06-07 13:20:50 -04:00
David Harris
2ae5ca19b5
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
ff62000e2c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
