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571 Commits

Author SHA1 Message Date
David Harris
f3c7025ade Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57 Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622 Broken state. address translation not working after changes to hptw to support atomic updates to PT. 2022-02-16 23:37:36 -06:00
Ross Thompson
c9e33208e3 Moved a few muxes around after sww changes. 2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b cleanup of signal names. 2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path. 2022-02-16 15:22:19 -06:00
David Harris
c23db6a31e Cleaned warning on HPTW default state 2022-02-16 17:40:13 +00:00
David Harris
01fa5c94bd Register file comments about reset 2022-02-16 17:21:05 +00:00
Ross Thompson
c56c4db47f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 09:48:16 -06:00
David Harris
aa990be959 removed csrn and all of its outputs because depricated 2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3 Mostly removed N_SUPPORTED 2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881 Just needed to recompile - all good. Now removed uretM because N-mode is depricated 2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
Ross Thompson
fcbb577f31 Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
David Harris
caa4d83e57 t push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-02-14 01:22:22 +00:00
Ross Thompson
86e117ea77 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5 More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63 More cache cleanup. 2022-02-13 12:38:39 -06:00
David Harris
f5678e25db Synthesis cleanup 2022-02-12 06:25:12 +00:00
David Harris
b537df2651 Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0 2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b More cache simplifications. 2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07 Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
Ross Thompson
20456097cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500 Fixed subtle and infrequenct bug. 
Loading buildroot at 483M instructions started with a spill + ITLBMiss.  The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation.  However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation.  Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
 2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60 Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618 Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
Ross Thompson
f23817bf69 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9 Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154 More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
2a989e6d05 More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7 Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22 Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
01126535db Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
7133e790ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 17:52:15 -06:00
Ross Thompson
498388c636 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
8a49ec90d0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 15:43:18 -06:00
Ross Thompson
e0a605e95d Cleanup IFU. 2022-02-08 14:54:53 -06:00
Ross Thompson
d1d014bf1d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
Ross Thompson
13561c67bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
Ross Thompson
cecbb3362d rv32e works for now. Still need to optimize. 2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f Moved some muxes back into the bp. 2022-02-08 14:17:44 -06:00
David Harris
3e16730226 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
d5d9bb9d4d Temporary commit which gets the no branch predictor implementation working. 2022-02-08 14:13:55 -06:00
Ross Thompson
3cd067ac6a Finished merge. 2022-02-08 11:36:24 -06:00
Ross Thompson
492c1473f3 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
David Harris
096242a6d8 Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
Ross Thompson
190d619940 cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
ca459a5915 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
494802b2e1 more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
23a60d9875 Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
fcd43ea004 more cleanup. 2022-02-07 13:29:19 -06:00
Ross Thompson
e72d54ea98 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
a6a7779ec0 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
7f732eb571 More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
be67c4d559 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
f1781c6bc8 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473 Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
c21eb67a07 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
David Harris
0feb624bab Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
Ross Thompson
308cc34d6f Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
Ross Thompson
1766c0f5ba Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5 Cleanup. 2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533 Moved the hwdata mux back into the busdp. 2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a Merged together the two sub cache line read muxes. 
One mux was used for loads and the other for eviction.
 2022-02-04 22:30:04 -06:00
David Harris
23868a33bc Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
Ross Thompson
c846368537 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10 Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6 Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
c3122ce214 sram1rw cleanup 2022-02-03 18:03:22 +00:00
David Harris
0e1d784b60 sram1rw cleanup 2022-02-03 17:50:23 +00:00
David Harris
eb8dd5e7d7 cachereplacementpolicy cleanup 2022-02-03 17:19:14 +00:00
David Harris
5f7326368e cachereplacementpolicy cleanup 2022-02-03 17:18:48 +00:00
David Harris
9b6a4d1d52 cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
7a8cc5ef21 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
0fbc32204c cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
c22f7eb11c cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
e92461159d cache cleanup 2022-02-03 15:36:11 +00:00
David Harris
9e0055cbb9 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73 changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
c12407ba6a Removed Busybear dependencies 2022-02-02 20:28:21 +00:00
Ross Thompson
910d16b642 More cleanup of IFU. 2022-02-01 14:32:27 -06:00
Ross Thompson
a9b4f9b1e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
99bb281944 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Ross Thompson
dce9ee12b4 IFU and LSU now share the same busdp module. 2022-01-31 16:25:41 -06:00
Ross Thompson
a04aa283cb partial ifu cleanup. 2022-01-31 16:08:53 -06:00
Ross Thompson
b05abc1795 cleanup. 2022-01-31 13:29:04 -06:00
Ross Thompson
d2ab17e1af Repaired linux-wave.do 2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5 Repaired wavefile and fixed modelsim warning. 2022-01-31 12:34:17 -06:00
Ross Thompson
1476a79ea2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-31 12:17:37 -06:00
Ross Thompson
fa8914a830 Cleanup busdp. 2022-01-31 12:17:07 -06:00
Ross Thompson
7c3d6bbdb4 Moved lsu virtual memory logic into separate module. 2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2 Removed unused signals in the LSU. 2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184 Moved atomic logic to own module. 2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183 Encapsulated the bus data path into a separate module. 2022-01-31 10:15:48 -06:00
David Harris
2d112698b7 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
Ross Thompson
d52c5b0393 LSU and IFU cleanup. 2022-01-28 15:26:06 -06:00
Ross Thompson
de0bef4f5b Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
147d71fd46 Clean up of mmu instances in IFU and LSU. 2022-01-28 14:02:05 -06:00
Ross Thompson
4a8d0cb981 Moved spills to own module. 2022-01-28 13:40:35 -06:00
Ross Thompson
7fedc6b878 Cleaned up the InstrMisalignedFault. 2022-01-28 13:19:24 -06:00
Ross Thompson
1bb8d36308 Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
87aa0724a2 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
1c22077841 Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13 Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
75c33bc6c9 BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. 2022-01-27 07:59:59 -06:00
Ross Thompson
c3a78553be Removed mux in PCNextF logic. Minor IFU improvements. 2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03 IFU simplifications. 2022-01-26 13:54:59 -06:00
Ross Thompson
728e46a794 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
David Harris
22c84dcd80 simpleram simplification 2022-01-25 19:46:13 +00:00
David Harris
8bf73d0eb3 simpleram simplification 2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f simpleram simplification 2022-01-25 18:26:31 +00:00
David Harris
7ac44cb3fc simpleram address simplification 2022-01-25 18:17:33 +00:00
David Harris
5eb71a3bbe simpleram address simplification 2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6 simpleram clk and reset simplification 2022-01-25 17:34:15 +00:00
David Harris
5cb879129e Start of IFU cleanup 2022-01-25 17:31:53 +00:00
Ross Thompson
4d4d9ac8cf Added spill support back into the IROM IFU. 2022-01-21 15:50:54 -06:00
Ross Thompson
4ecc2d029a Changed the IROM and DTIM memories to behave like edge-triggered srams. 2022-01-21 15:42:54 -06:00
Ross Thompson
ec44774c77 Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv 2022-01-20 16:39:54 -06:00
David Harris
ca1f7ce5d3 Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
Ross Thompson
05ebadacad Added PCNextF and PostSpillInstrRawF to ila. 2022-01-19 14:05:14 -06:00
Ross Thompson
5cf686429d Merged in the debug ila updates. 2022-01-18 17:29:21 -06:00
Ross Thompson
2508b9d35a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-18 17:19:59 -06:00
Ross Thompson
fdc17f5017 Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes. 2022-01-18 17:19:33 -06:00
David Harris
de7b9c127e Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
David Harris
8b62130070 lsu cleanup down to 346 lines 2022-01-15 01:19:44 +00:00
David Harris
b967bcede2 LSU Cleanup 2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
David Harris
b0263012e8 LSU cleanup 2022-01-15 00:11:30 +00:00
David Harris
4c5962095e LSU cleanup 2022-01-15 00:03:03 +00:00
David Harris
37bf5347cf LSU cleanup 2022-01-14 23:55:27 +00:00
Ross Thompson
dd1ebb75f0 Fixed spillthreshold warning. 2022-01-14 17:23:39 -06:00
Ross Thompson
9d2a79f180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-14 17:16:53 -06:00
David Harris
380e990def moved fp to tests 2022-01-14 23:05:59 +00:00
David Harris
291deb5c39 LSU partitioning 2022-01-14 23:02:28 +00:00
Ross Thompson
db519a0dca Cleanup IFU comments. 2022-01-14 15:06:30 -06:00
Ross Thompson
a70e12ad75 Optimization in the ifu. Please note this optimization is not strictly correct, 
but is possible.  See comments in the ifu source code for details.
 2022-01-14 12:16:48 -06:00
Ross Thompson
a549079672 More ifu cleanup. 2022-01-14 11:19:12 -06:00
Ross Thompson
ce937a35a8 Added tim only test to regression-wally. Minor cleanup to ifu. 2022-01-14 11:13:06 -06:00
Ross Thompson
5726b5b640 Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
Ross Thompson
9f7e3f147b Partial local dtim in lsu configuration. 2022-01-13 17:50:31 -06:00
Ross Thompson
0b06fa12ef Merge branch 'testDivInterruptInterlock' into main 2022-01-13 11:21:48 -06:00
Ross Thompson
93cb24476f Fixed interger divide so it can be interrupted. 2022-01-13 11:16:50 -06:00
Ross Thompson
4bcabd1a55 Removed unused inputs to hptw. 2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92 Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu. 2022-01-12 17:41:39 -06:00
Ross Thompson
861450c4d6 Fixed support to allow spills and no icache. 2022-01-12 17:25:16 -06:00
Ross Thompson
000d713cb5 Better solution to the integer divider interrupt interaction. 2022-01-12 14:22:18 -06:00
Ross Thompson
26fb09c868 Added additional fsm to ILA. 2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4 Possible fix for the TrapM DTLBMiss suppression. 2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. 
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
 2022-01-12 14:17:16 -06:00
Ross Thompson
48c036a923 Oups. My hack for DivE interrupt prevention was wrong. 2022-01-12 14:17:16 -06:00
Ross Thompson
796316495d Hack "fix" to prevent interrupt from occuring during an integer divide. 
This is not the desired solution but will allow continued debuging of linux.
 2022-01-12 14:17:16 -06:00
Ross Thompson
55456e465c Added icache access and icache miss to performance counters. 2022-01-09 22:56:56 -06:00
Ross Thompson
b6ae6fea27 Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu 
only at the start of a request.  Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm.  On a miss with write back, the inital fetch is handled correctly.  However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.

The solution is to modify how cpu requests are suppressed.  Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
 2022-01-07 17:55:34 -06:00
David Harris
3d2671a8b0 Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
David Harris
913a78323c moved proposed-sdc 2022-01-07 12:44:21 +00:00
David Harris
6c0cd5ef20 piplined directory cleanup 2022-01-07 12:43:50 +00:00
David Harris
8481c93e1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-07 05:39:16 +00:00
Ross Thompson
de3bbd3fe0 Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata. 
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
 2022-01-06 23:28:02 -06:00
David Harris
261882bf78 Used .* in wrapper 2022-01-07 05:23:42 +00:00
Ross Thompson
fa0080ca70 Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 
assign from the input non translated virtual address.  Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address.  This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
 2022-01-06 23:19:09 -06:00
David Harris
2df92af488 Capitalized LSU and IFU, changed MulDiv to MDU 2022-01-07 04:30:00 +00:00
David Harris
27c1d73cb1 Code cleanup 2022-01-07 04:07:04 +00:00
Ross Thompson
5402b55c44 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-06 17:19:20 -06:00
Ross Thompson
0438975e27 Minor optimization to cache replacement. 2022-01-06 17:19:14 -06:00
David Harris
6fafabbfad Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 23:04:33 +00:00
David Harris
ae64b859c3 Fixed multiplier nan boxing bug 2022-01-06 23:03:29 +00:00
Katherine Parry
631d05dcdc some FPU test fixes 2022-01-06 23:03:20 +00:00
Ross Thompson
e0740034f0 Clean up of cachefsm. 2022-01-06 16:32:49 -06:00
David Harris
3bfe23bc75 More FP unpacking fix 2022-01-06 22:22:22 +00:00
David Harris
770780e394 Floating point test cleanup 2022-01-06 21:45:16 +00:00
David Harris
a5a89e58a8 Fixed unpacking bug; regression runs again 2022-01-06 18:22:30 +00:00
David Harris
eff9cec415 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
David Harris
aca26de498 FPU debug and configurable logic cleanup 2022-01-06 18:10:25 +00:00
Ross Thompson
f604a0d79e cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv. 2022-01-05 22:56:18 -06:00
Ross Thompson
a4afc1bc54 More name cleanup in cache. 2022-01-05 22:37:53 -06:00
Ross Thompson
e74e8c2e86 Changed names of address in caches. 
Removed old cache files.
 2022-01-05 22:19:36 -06:00
Ross Thompson
1ab3a17ff7 Updates to support fpga. 2022-01-05 18:07:23 -06:00
Ross Thompson
9ea34e390a Fixed xilinx synth error with $error in extend.sv 2022-01-05 17:48:08 -06:00
Ross Thompson
de32930e63 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-05 16:57:29 -06:00
Ross Thompson
da585b30f9 Slower but correct implementation of flush. 2022-01-05 16:57:22 -06:00
David Harris
90dd961ea5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-05 22:10:33 +00:00
David Harris
07932ad0aa Replaced exe2memfile with SiFive elf2hex 2022-01-05 22:10:26 +00:00
Ross Thompson
7086a0ed08 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-05 14:15:27 -06:00
Ross Thompson
cc51a27a34 Fixed bug with flush dirty not cleared in the correct cache line. 2022-01-05 14:14:01 -06:00
David Harris
d17a305538 Finished removing generate statements 2022-01-05 16:41:17 +00:00
David Harris
6d4714651c Removed more generate statements 2022-01-05 16:25:08 +00:00
David Harris
da5ead23bf Removed more generate statements 2022-01-05 16:01:03 +00:00
David Harris
d66f7c841b Removed generate statements 2022-01-05 14:35:25 +00:00
Ross Thompson
98be8201b2 Renamed most signals inside cache.sv so they are agnostic to i or d. 2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6 the i and d caches now share common verilog. 2022-01-04 23:40:37 -06:00
Ross Thompson
13dbf3cc0f parameterized the caches with the goal of using common rtl for both i and d caches. 2022-01-04 22:40:51 -06:00
Ross Thompson
888a60d8d6 Switched block for line in caches. 2022-01-04 22:08:18 -06:00
Ross Thompson
cb301a78ad Fixed bug where last line of dcache was not written back to memory on dcache flush. 2022-01-04 21:55:48 -06:00
Ross Thompson
ecc7bf5237 Fixed dcache flush. 2022-01-04 18:40:58 -06:00
David Harris
d1a7416028 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 19:47:51 +00:00
David Harris
115287adc8 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00