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simpleram clk and reset simplification

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This commit is contained in:
David Harris 2022-01-25 17:34:15 +00:00
parent 5cb879129e
commit d9888c91a6
3 changed files with 6 additions and 16 deletions
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8
pipelined/src/generic/flop/simpleram.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh"
module simpleram #(parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn,
input logic clk,
input logic HSELRam,
input logic [31:0] HADDR,
input logic HWRITE,
@ -56,15 +56,15 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
flopenr #(32) haddrreg(HCLK, 1'b0, 1'b1, HADDR, A);
flopenr #(32) haddrreg(clk, 1'b0, 1'b1, HADDR, A);
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw
always_ff @(posedge HCLK) begin
always_ff @(posedge clk) begin
if (HWRITE & |HTRANS) RAM[A[31:3]] <= #1 HWDATA;
end
end else begin
always_ff @(posedge HCLK) begin:ramrw
always_ff @(posedge clk) begin:ramrw
if (HWRITE & |HTRANS) RAM[A[31:2]] <= #1 HWDATA;
end
end

12
pipelined/src/ifu/ifu.sv
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@ -235,21 +235,11 @@ module ifu (
simpleram #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK(clk), .HRESETn(~reset),
.clk,
.HSELRam(1'b1), .HADDR(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
.HWRITE(1'b0), .HREADY(1'b1),
.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
.HRESPRam(), .HREADYRam());
/* -----\/----- EXCLUDED -----\/-----
ram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK(clk), .HRESETn(~reset),
.HSELRam(1'b1), .HADDR(PCNextF[31:0]),
.HWRITE(1'b0), .HREADY(1'b1),
.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
.HRESPRam(), .HREADYRam());
-----/\----- EXCLUDED -----/\----- */
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
assign BusStall = 0;
assign IFUBusRead = 0;

2
pipelined/src/lsu/lsu.sv
View File

@ -246,7 +246,7 @@ module lsu (
if (`MEM_DTIM) begin : dtim
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK(clk), .HRESETn(~reset),
.clk,
.HSELRam(1'b1), .HADDR(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
.HWRITE(LSURWM[0]), .HREADY(1'b1),
.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),