cvw/pipelined/src
2022-01-14 17:23:39 -06:00
..
cache Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
ebu Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
fpu Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
generic Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
hazard Fixed interger divide so it can be interrupted. 2022-01-13 11:16:50 -06:00
ieu Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
ifu Fixed spillthreshold warning. 2022-01-14 17:23:39 -06:00
lsu moved fp to tests 2022-01-14 23:05:59 +00:00
mmu Removed unused inputs to hptw. 2022-01-13 11:04:48 -06:00
muldiv Better solution to the integer divider interrupt interaction. 2022-01-12 14:22:18 -06:00
privileged Better solution to the integer divider interrupt interaction. 2022-01-12 14:22:18 -06:00
uncore Partial local dtim in lsu configuration. 2022-01-13 17:50:31 -06:00
wally Better solution to the integer divider interrupt interaction. 2022-01-12 14:22:18 -06:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00