cvw/pipelined/src
2022-01-13 11:04:48 -06:00
..
cache Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
ebu Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
fpu Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
generic Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
hazard Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
ieu Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
ifu Fixed support to allow spills and no icache. 2022-01-12 17:25:16 -06:00
lsu Removed unused inputs to hptw. 2022-01-13 11:04:48 -06:00
mmu Removed unused inputs to hptw. 2022-01-13 11:04:48 -06:00
muldiv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
privileged Added icache access and icache miss to performance counters. 2022-01-09 22:56:56 -06:00
uncore Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu. 2022-01-12 17:41:39 -06:00
wally Added icache access and icache miss to performance counters. 2022-01-09 22:56:56 -06:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00