mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
This commit is contained in:
Ross Thompson
parent
9f7e3f147b
commit
5726b5b640
@ -50,9 +50,9 @@
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DTIM 1
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`define MEM_DTIM 0
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`define MEM_DCACHE 1
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`define MEM_IROM 1
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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@ -48,9 +48,9 @@
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DTIM 1
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`define MEM_DTIM 0
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`define MEM_DCACHE 1
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`define MEM_IROM 1
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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@ -50,9 +50,9 @@
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DTIM 1
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`define MEM_DTIM 0
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`define MEM_DCACHE 1
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`define MEM_IROM 1
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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@ -51,7 +51,7 @@
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`define UARCH_SINGLECYCLE 0
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`define MEM_DTIM 0
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`define MEM_DCACHE 1
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`define MEM_IROM 1
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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@ -52,7 +52,7 @@
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`define MEM_DTIM 0
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`define MEM_DCACHE 0
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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@ -51,9 +51,9 @@
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DTIM 1
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`define MEM_DTIM 0
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`define MEM_DCACHE 1
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`define MEM_IROM 1
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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@ -52,7 +52,7 @@
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`define UARCH_SINGLECYCLE 0
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`define MEM_DTIM 0
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`define MEM_DCACHE 1
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`define MEM_IROM 1
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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@ -50,9 +50,9 @@
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DTIM 1
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`define MEM_DTIM 0
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`define MEM_DCACHE 1
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`define MEM_IROM 1
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`define MEM_IROM 0
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`define MEM_ICACHE 1
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`define MEM_VIRTMEM 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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56
pipelined/regression/wally-harvard.do
Normal file
56
pipelined/regression/wally-harvard.do
Normal file
@ -0,0 +1,56 @@
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# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined.do ../config/rv32ic
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#switch $argc {
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# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
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# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
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#}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-harvard.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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vopt +acc work.testbench -G TEST=$2 -o workopt
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vsim workopt
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view wave
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-- display input and output signals as hexidecimal values
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#do ./wave-dos/peripheral-waves.do
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add log -recursive /*
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do wave.do
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-- Run the Simulation
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#run 3600
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run -all
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#quit
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#noview ../testbench/testbench-imperas.sv
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noview ../testbench/testbench.sv
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view wave
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80
pipelined/src/generic/flop/simpleram.sv
Normal file
80
pipelined/src/generic/flop/simpleram.sv
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@ -0,0 +1,80 @@
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///////////////////////////////////////////
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// simpleram.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: On-chip SIMPLERAM, external to hart
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module simpleram #(parameter BASE=0, RANGE = 65535) (
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input logic HCLK, HRESETn,
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input logic HSELRam,
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input logic [31:0] HADDR,
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input logic HWRITE,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [`XLEN-1:0] HWDATA,
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output logic [`XLEN-1:0] HREADRam,
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output logic HRESPRam, HREADYRam
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);
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localparam MemStartAddr = BASE>>(1+`XLEN/32);
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localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
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logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
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logic [31:0] HWADDR, A;
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logic [`XLEN-1:0] HREADRam0;
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logic prevHREADYRam, risingHREADYRam;
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logic initTrans;
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logic memwrite;
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logic [3:0] busycount;
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/* verilator lint_off WIDTH */
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if (`XLEN == 64) begin:ramrw
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always_ff @(posedge HCLK) begin
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if (HWRITE & |HTRANS) RAM[HADDR[31:3]] <= #1 HWDATA;
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end
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end else begin
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always_ff @(posedge HCLK) begin:ramrw
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if (HWRITE & |HTRANS) RAM[HADDR[31:2]] <= #1 HWDATA;
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end
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end
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// read
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if(`XLEN == 64) begin: ramr
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assign HREADRam0 = RAM[HADDR[31:3]];
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end else begin
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assign HREADRam0 = RAM[HADDR[31:2]];
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end
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/* verilator lint_on WIDTH */
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assign HREADRam = HREADRam0;
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endmodule
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@ -285,18 +285,23 @@ module ifu (
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if (`MEM_IROM == 1) begin : irom
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ram #(
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logic [`XLEN-1:0] FinalInstrRawF_FIXME;
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simpleram #(
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.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.HCLK(clk), .HRESETn(~reset),
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.HSELRam(1'b1), .HADDR(PCPF[31:0]),
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.HWRITE(1'b0), .HREADY(1'b1),
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.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF),
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.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
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.HRESPRam(), .HREADYRam());
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assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
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assign BusStall = 0;
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assign IFUBusRead = 0;
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assign ICacheBusAck = 0;
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assign SelUncachedAdr = 0;
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assign IFUBusAdr = 0;
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end else begin : bus
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genvar index;
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@ -359,7 +359,7 @@ module lsu
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if (`MEM_DTIM == 1) begin : dtim
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ram #(
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simpleram #(
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.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.HCLK(clk), .HRESETn(~reset),
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.HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]),
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476
pipelined/testbench/testbench-harvard.sv
Normal file
476
pipelined/testbench/testbench-harvard.sv
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@ -0,0 +1,476 @@
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///////////////////////////////////////////
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// testbench.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the riscv-arch-test and Imperas suites
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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`include "tests.vh"
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module testbench;
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parameter TESTSPERIPH = 0; // set to 0 for regression
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parameter TESTSPRIV = 0; // set to 0 for regression
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parameter DEBUG=0;
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parameter TEST="none";
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logic clk;
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logic reset_ext, reset;
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parameter SIGNATURESIZE = 5000000;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:SIGNATURESIZE];
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logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests[];
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logic [3:0] dummy;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`XLEN-1:0] PCW;
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logic DCacheFlushDone, DCacheFlushStart;
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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// check assertions for a legal configuration
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riscvassertions riscvassertions();
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// pick tests based on modes supported
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initial begin
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$display("TEST is %s", TEST);
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//tests = '{};
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if (`XLEN == 64) begin // RV64
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case (TEST)
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"arch64i": tests = arch64i;
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"arch64priv": tests = arch64priv;
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"arch64c": if (`C_SUPPORTED)
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if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
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else tests = {arch64c};
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"arch64m": if (`M_SUPPORTED) tests = arch64m;
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"arch64d": if (`D_SUPPORTED) tests = arch64d;
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"imperas64i": tests = imperas64i;
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"imperas64p": tests = imperas64p;
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// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
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"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
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"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
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"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
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"imperas64a": if (`A_SUPPORTED) tests = imperas64a;
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"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
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else tests = imperas64iNOc;
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"testsBP64": tests = testsBP64;
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"wally64i": tests = wally64i; // *** redo
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"wally64priv": tests = wally64priv;// *** redo
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"imperas64periph": tests = imperas64periph;
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endcase
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end else begin // RV32
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case (TEST)
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"arch32i": tests = arch32i;
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"arch32priv": tests = arch32priv;
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"arch32c": if (`C_SUPPORTED)
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if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
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else tests = {arch32c};
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"arch32m": if (`M_SUPPORTED) tests = arch32m;
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"arch32f": if (`F_SUPPORTED) tests = arch32f;
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"imperas32i": tests = imperas32i;
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"imperas32p": tests = imperas32p;
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// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
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"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
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"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
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"imperas32a": if (`A_SUPPORTED) tests = imperas32a;
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"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
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else tests = imperas32iNOc;
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"wally32i": tests = wally32i; // *** redo
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"wally32priv": tests = wally32priv; // *** redo
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"imperas32periph": tests = imperas32periph;
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endcase
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end
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if (tests.size() == 0) begin
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$display("TEST %s not supported in this configuration", TEST);
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$stop;
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end
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end
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string signame, memfilename, pathname;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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logic SDCCLK;
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logic SDCCmdIn;
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logic SDCCmdOut;
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logic SDCCmdOE;
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logic [3:0] SDCDatIn;
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logic HREADY;
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logic HSELEXT;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
localparam integer MemStartAddr = `RAM_BASE>>(1+`XLEN/32);
|
||||
localparam integer MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32);
|
||||
|
||||
initial
|
||||
begin
|
||||
test = 1;
|
||||
totalerrors = 0;
|
||||
testadr = 0;
|
||||
// fill memory with defined values to reduce Xs in simulation
|
||||
// Quick note the memory will need to be initialized. The C library does not
|
||||
// guarantee the initialized reads. For example a strcmp can read 6 byte
|
||||
// strings, but uses a load double to read them in. If the last 2 bytes are
|
||||
// not initialized the compare results in an 'x' which propagates through
|
||||
// the design.
|
||||
if (`XLEN == 32) meminit = 32'hFEDC0123;
|
||||
else meminit = 64'hFEDCBA9876543210;
|
||||
// *** broken because DTIM also drives RAM
|
||||
if (`TESTSBP) begin
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
|
||||
dut.uncore.ram.ram.RAM[i] = meminit;
|
||||
end
|
||||
end
|
||||
// read test vectors into memory
|
||||
pathname = tvpaths[tests[0].atoi()];
|
||||
/* if (tests[0] == `IMPERASTEST)
|
||||
pathname = tvpaths[0];
|
||||
else pathname = tvpaths[1]; */
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
|
||||
$readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
// if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
//`ifdef `MEM_IROM
|
||||
// $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
|
||||
// $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
//`endif
|
||||
// if(`MEM_IROM == 1) begin
|
||||
// $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
|
||||
$readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
// end
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset_ext = 1; # 42; reset_ext = 0;
|
||||
end
|
||||
|
||||
// generate clock to sequence tests
|
||||
always
|
||||
begin
|
||||
clk = 1; # 5; clk = 0; # 5;
|
||||
// if ($time % 100000 == 0) $display("Time is %0t", $time);
|
||||
end
|
||||
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (DCacheFlushDone) begin
|
||||
|
||||
#600; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
sig32[i] = 'bx;
|
||||
end
|
||||
|
||||
// read signature, reformat in 64 bits if necessary
|
||||
signame = {pathname, tests[test], ".signature.output"};
|
||||
$readmemh(signame, sig32);
|
||||
i = 0;
|
||||
while (i < SIGNATURESIZE) begin
|
||||
if (`XLEN == 32) begin
|
||||
signature[i] = sig32[i];
|
||||
i = i+1;
|
||||
end else begin
|
||||
signature[i/2] = {sig32[i+1], sig32[i]};
|
||||
i = i + 2;
|
||||
end
|
||||
if (sig32[i-1] === 'bx) begin
|
||||
if (i == 1) begin
|
||||
i = SIGNATURESIZE+1; // flag empty file
|
||||
$display(" Error: empty test file");
|
||||
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
|
||||
end
|
||||
end
|
||||
|
||||
// Check errors
|
||||
errors = (i == SIGNATURESIZE+1); // error if file is empty
|
||||
i = 0;
|
||||
testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8);
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
// *** have to figure out how to exclude shadowram when not using a dcache.
|
||||
if (signature[i] !== dut.hart.lsu.dtim.ram.RAM[testadr+i] &
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
// kind of hacky test for garbage right now
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
|
||||
//tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
|
||||
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.hart.lsu.dtim.ram.RAM[testadr+i], signature[i]);
|
||||
$stop;//***debug
|
||||
end
|
||||
end
|
||||
i = i + 1;
|
||||
end
|
||||
/* verilator lint_on INFINITELOOP */
|
||||
if (errors == 0) begin
|
||||
$display("%s succeeded. Brilliant!!!", tests[test]);
|
||||
end
|
||||
else begin
|
||||
$display("%s failed with %d errors. :(", tests[test], errors);
|
||||
totalerrors = totalerrors+1;
|
||||
end
|
||||
test = test + 2;
|
||||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||
$stop;
|
||||
end
|
||||
else begin
|
||||
//pathname = tvpaths[tests[0]];
|
||||
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
//$readmemh(memfilename, dut.uncore.ram.ram.RAM);
|
||||
$readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
//if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
`ifdef `MEM_IROM
|
||||
$display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
|
||||
$readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
`endif
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
$readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
//if(`MEM_IROM == 1) $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
$display("Read memfile %s", memfilename);
|
||||
reset_ext = 1; # 47; reset_ext = 0;
|
||||
end
|
||||
end
|
||||
end // always @ (negedge clk)
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1) begin : FunctionName
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
.clk(clk),
|
||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
// Termination condition
|
||||
// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
|
||||
// or sw gp,-56(t0) for new Imperas tests
|
||||
// or sd gp, -56(t0)
|
||||
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
|
||||
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
|
||||
if (`ZICSR_SUPPORTED) assign ecf = dut.hart.priv.priv.EcallFaultM;
|
||||
else assign ecf = 0;
|
||||
assign DCacheFlushStart = ecf &
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 |
|
||||
(dut.hart.ieu.dp.regf.we3 &
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &
|
||||
dut.hart.ieu.dp.regf.wd3 == 1)) |
|
||||
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
|
||||
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1)
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module riscvassertions;
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support");
|
||||
assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
|
||||
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
|
||||
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
/* verilator lint_on STMTDLY */
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
module DCacheFlushFSM
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
genvar adr;
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
if(`MEM_DCACHE) begin
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
|
||||
localparam integer linebytelen = testbench.dut.hart.lsu.dcache.dcache.LINEBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.LINELEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer loglinebytelen = $clog2(linebytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + loglinebytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.loglinebytelen(loglinebytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
integer i, j, k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
flop #(1) doneReg(.clk, .d(start), .q(done));
|
||||
endmodule
|
||||
|
||||
module copyShadow
|
||||
#(parameter tagstart, loglinebytelen)
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [`XLEN-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [`XLEN-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
output logic CacheDirty);
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(start) begin
|
||||
CacheTag = tag;
|
||||
CacheValid = valid;
|
||||
CacheDirty = dirty;
|
||||
CacheData = data;
|
||||
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8));
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user