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https://github.com/openhwgroup/cvw
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Fixed bug with flush dirty not cleared in the correct cache line.
This commit is contained in:
Ross Thompson
parent
98be8201b2
commit
cc51a27a34
16
pipelined/src/cache/cache.sv
vendored
16
pipelined/src/cache/cache.sv
vendored
@ -75,7 +75,7 @@ module cache #(parameter integer LINELEN,
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localparam integer FlushAdrThreshold = NUMLINES;
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logic [1:0] SelAdrM;
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logic [1:0] SelAdr;
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logic [INDEXLEN-1:0] RAdr;
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logic [LINELEN-1:0] SRAMWriteData;
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logic SetValid, ClearValid;
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@ -104,6 +104,8 @@ module cache #(parameter integer LINELEN,
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logic [INDEXLEN-1:0] FlushAdr;
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logic [INDEXLEN-1:0] FlushAdrP1;
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logic [INDEXLEN-1:0] FlushAdrQ;
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logic [INDEXLEN-1:0] FlushAdrMux;
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logic SelLastFlushAdr;
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logic FlushAdrCntEn;
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logic FlushAdrCntRst;
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logic FlushAdrFlag;
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@ -124,9 +126,13 @@ module cache #(parameter integer LINELEN,
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mux3 #(INDEXLEN)
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AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d2(FlushAdr),
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.s(SelAdrM),
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.d2(FlushAdrMux),
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.s(SelAdr),
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.y(RAdr));
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mux2 #(INDEXLEN)
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FlushAdrSelMux(.d0(FlushAdr), .d1(FlushAdrQ), .s(SelLastFlushAdr),
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.y(FlushAdrMux));
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cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
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.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
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@ -270,11 +276,11 @@ module cache #(parameter integer LINELEN,
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cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
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.RW, .Atomic, .CPUBusy, .CacheableM, .IgnoreRequest,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdrM, .SetValid,
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.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
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.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
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.SRAMLineWriteEnableM, .SelEvict, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
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.FlushWayCntRst, .FlushAdrFlag, .FlushCache,
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.FlushWayCntRst, .FlushAdrFlag, .FlushCache, .SelLastFlushAdr,
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.VDWriteEnable, .LRUWriteEn);
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64
pipelined/src/cache/cachefsm.sv
vendored
64
pipelined/src/cache/cachefsm.sv
vendored
@ -50,12 +50,12 @@ module cachefsm
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output logic CacheMiss,
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output logic CacheAccess,
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// Bus outputs
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output logic CacheCommitted,
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output logic CacheCommitted,
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output logic CacheWriteLine,
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output logic CacheFetchLine,
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// dcache internals
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output logic [1:0] SelAdrM,
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output logic [1:0] SelAdr,
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output logic SetValid,
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output logic ClearValid,
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output logic SetDirty,
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@ -65,6 +65,7 @@ module cachefsm
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output logic SelEvict,
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output logic LRUWriteEn,
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output logic SelFlush,
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output logic SelLastFlushAdr,
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output logic FlushAdrCntEn,
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output logic FlushWayCntEn,
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output logic FlushAdrCntRst,
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@ -107,7 +108,7 @@ module cachefsm
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// next state logic and some state ouputs.
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always_comb begin
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CacheStall = 1'b0;
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SelAdrM = 2'b00;
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SelAdr = 2'b00;
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SetValid = 1'b0;
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ClearValid = 1'b0;
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SetDirty = 1'b0;
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@ -125,12 +126,13 @@ module cachefsm
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NextState = STATE_READY;
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CacheFetchLine = 1'b0;
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CacheWriteLine = 1'b0;
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SelLastFlushAdr = 1'b0;
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case (CurrState)
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STATE_READY: begin
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CacheStall = 1'b0;
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SelAdrM = 2'b00;
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SelAdr = 2'b00;
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SRAMWordWriteEnableM = 1'b0;
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SetDirty = 1'b0;
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LRUWriteEn = 1'b0;
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@ -143,7 +145,7 @@ module cachefsm
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// PTW ready the CPU will stall.
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// The page table walker asserts it's control 1 cycle
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// after the TLBs miss.
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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NextState = STATE_READY;
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end
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@ -151,19 +153,19 @@ module cachefsm
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else if(FlushCache) begin
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NextState = STATE_FLUSH;
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CacheStall = 1'b1;
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SelAdrM = 2'b10;
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SelAdr = 2'b10;
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FlushAdrCntRst = 1'b1;
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FlushWayCntRst = 1'b1;
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end
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// amo hit
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else if(Atomic[1] & (&RW) & CacheableM & CacheHit) begin
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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CacheStall = 1'b0;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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end
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else begin
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SRAMWordWriteEnableM = 1'b1;
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@ -179,7 +181,7 @@ module cachefsm
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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@ -187,7 +189,7 @@ module cachefsm
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end
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// write hit valid cached
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else if (RW[0] & CacheableM & CacheHit) begin
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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CacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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SetDirty = 1'b1;
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@ -195,7 +197,7 @@ module cachefsm
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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@ -212,7 +214,7 @@ module cachefsm
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STATE_MISS_FETCH_WDV: begin
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CacheStall = 1'b1;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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if (CacheBusAck) begin
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NextState = STATE_MISS_FETCH_DONE;
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@ -223,7 +225,7 @@ module cachefsm
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STATE_MISS_FETCH_DONE: begin
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CacheStall = 1'b1;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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if(VictimDirty) begin
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NextState = STATE_MISS_EVICT_DIRTY;
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CacheWriteLine = 1'b1;
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@ -236,14 +238,14 @@ module cachefsm
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SRAMLineWriteEnableM = 1'b1;
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CacheStall = 1'b1;
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NextState = STATE_MISS_READ_WORD;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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SetValid = 1'b1;
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ClearDirty = 1'b1;
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//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
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end
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STATE_MISS_READ_WORD: begin
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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CacheStall = 1'b1;
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if (RW[0] & ~Atomic[1]) begin // handles stores and amo write.
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NextState = STATE_MISS_WRITE_WORD;
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@ -255,12 +257,12 @@ module cachefsm
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end
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STATE_MISS_READ_WORD_DELAY: begin
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//SelAdrM = 2'b01;
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//SelAdr = 2'b01;
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SRAMWordWriteEnableM = 1'b0;
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SetDirty = 1'b0;
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LRUWriteEn = 1'b0;
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if(&RW & Atomic[1]) begin // amo write
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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end
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@ -274,7 +276,7 @@ module cachefsm
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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@ -285,11 +287,11 @@ module cachefsm
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STATE_MISS_WRITE_WORD: begin
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SRAMWordWriteEnableM = 1'b1;
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SetDirty = 1'b1;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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@ -298,7 +300,7 @@ module cachefsm
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STATE_MISS_EVICT_DIRTY: begin
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CacheStall = 1'b1;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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SelEvict = 1'b1;
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if(CacheBusAck) begin
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NextState = STATE_MISS_WRITE_CACHE_LINE;
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@ -309,10 +311,10 @@ module cachefsm
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STATE_CPU_BUSY: begin
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SelAdrM = 2'b00;
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SelAdr = 2'b00;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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@ -320,7 +322,7 @@ module cachefsm
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end
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STATE_CPU_BUSY_FINISH_AMO: begin
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SelAdrM = 2'b01;
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SelAdr = 2'b01;
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SRAMWordWriteEnableM = 1'b0;
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SetDirty = 1'b0;
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LRUWriteEn = 1'b0;
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@ -337,15 +339,17 @@ module cachefsm
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STATE_FLUSH: begin
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CacheStall = 1'b1;
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SelAdrM = 2'b10;
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SelAdr = 2'b10;
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SelFlush = 1'b1;
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FlushAdrCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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SelLastFlushAdr = 1'b0;
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if(VictimDirty) begin
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NextState = STATE_FLUSH_WRITE_BACK;
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FlushAdrCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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CacheWriteLine = 1'b1;
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SelLastFlushAdr = 1'b1;
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end else if (FlushAdrFlag) begin
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NextState = STATE_READY;
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CacheStall = 1'b0;
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@ -358,8 +362,9 @@ module cachefsm
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STATE_FLUSH_WRITE_BACK: begin
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CacheStall = 1'b1;
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SelAdrM = 2'b10;
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SelAdr = 2'b10;
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SelFlush = 1'b1;
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SelLastFlushAdr = 1'b1;
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if(CacheBusAck) begin
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NextState = STATE_FLUSH_CLEAR_DIRTY;
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end else begin
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@ -372,13 +377,14 @@ module cachefsm
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ClearDirty = 1'b1;
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VDWriteEnable = 1'b1;
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SelFlush = 1'b1;
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SelAdrM = 2'b10;
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SelAdr = 2'b10;
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FlushAdrCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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SelLastFlushAdr = 1'b0;
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if(FlushAdrFlag) begin
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NextState = STATE_READY;
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CacheStall = 1'b0;
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SelAdrM = 2'b00;
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SelAdr = 2'b00;
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end else begin
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NextState = STATE_FLUSH;
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FlushAdrCntEn = 1'b1;
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