cvw/pipelined/src
Ross Thompson fa0080ca70 Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
assign from the input non translated virtual address.  Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address.  This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
..
cache Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 2022-01-06 23:19:09 -06:00
ebu Removed more generate statements 2022-01-05 16:25:08 +00:00
fpu Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 23:04:33 +00:00
generic Fixed unpacking bug; regression runs again 2022-01-06 18:22:30 +00:00
hazard Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
ieu Floating point test cleanup 2022-01-06 21:45:16 +00:00
ifu Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 2022-01-06 23:19:09 -06:00
lsu Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 2022-01-06 23:19:09 -06:00
mmu Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 2022-01-06 23:19:09 -06:00
muldiv Removed generate statements 2022-01-05 14:35:25 +00:00
privileged Removed generate statements 2022-01-05 14:35:25 +00:00
uncore Replaced exe2memfile with SiFive elf2hex 2022-01-05 22:10:26 +00:00
wally Fixed multiplier nan boxing bug 2022-01-06 23:03:29 +00:00