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Optimization in the ifu. Please note this optimization is not strictly correct,
but is possible. See comments in the ifu source code for details.
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@ -96,7 +96,7 @@ module ifu (
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logic [`XLEN-1:0] PCD;
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic reset_q; // *** look at this later.
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//logic reset_q; // see comment below about PCNextF and icache.
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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logic [`XLEN-1:0] PCBPWrongInvalidate;
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@ -327,7 +327,7 @@ module ifu (
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// uses interlock fsm.
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assign IgnoreRequest = ITLBMissF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
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flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
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assign PrivilegedChangePCM = RetM | TrapM;
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@ -354,16 +354,26 @@ module ifu (
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
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.d1(PrivilegedNextPCM),
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.s(PrivilegedChangePCM),
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.y(PCNext3F));
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.y(UnalignedPCNextF));
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mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
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.d1(`RESET_VECTOR),
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.s(reset_q),
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.y(UnalignedPCNextF));
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flop #(1) resetReg (.clk(clk),
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.d(reset),
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.q(reset_q));
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//.y(PCNext3F));
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// This mux is not strictly speaking required. Because the icache takes in
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// PCNextF rather than PCPF, PCNextF should stay in reset while the cache
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// looks up the addresses. Without this mux PCNextF will increment + 2/4.
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// When the icache fsm is out of reset then it will report on the status
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// of PCF + 2/4. It will be a miss since this is the very first access.
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// On the next cycle the cache will start using PCPF to finish the read.
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// Because the granularity of a cache line +2/4 will always fit in the same
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// cache line so the mux is not required. I am leaving this comment and mux
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// a a reminder as to what is happening in case keep PCNextF at RESET_VECTOR
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// during reset becomes a requirement.
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//mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
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// .d1(`RESET_VECTOR),
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// .s(reset_q),
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// .y(UnalignedPCNextF));
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//flop #(1) resetReg (.clk(clk),
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// .d(reset),
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// .q(reset_q));
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM),
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