Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
2,084 Commits 5 Branches 2 Tags 53 MiB
c13e24743b
Commit Graph

551 Commits

Author SHA1 Message Date
bbracker
9469367da3 make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9 MSTATUS workaround 2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b workaround for ignoring MTIME 2021-06-20 02:26:39 -04:00
bbracker
3e32ba3684 make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
bbracker
f84a689c19 fixed PCtext error by using blocking assignments 2021-06-18 17:37:40 -04:00
bbracker
958f60c704 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
bbracker
8ae333a6b2 remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
72d8d34e3c allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
832e4fc7e3 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
e93e528aa1 changed parsedCSRs2] to parsedCSRs 2021-06-17 05:18:14 -04:00
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
David Harris
cfe5c27946 Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
46b2b19792 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
David Harris
b37bcc8e38 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
95cc70295b Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
b99b5f8e0e moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Kip Macsai-Goren
a84dd6dfc5 added tests for SV48 and translation off with vmem 2021-06-03 14:28:52 -04:00
James E. Stine
bccdd2c137 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
Ross Thompson
8f9680556f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346 Now have global history working correctly. 2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Katherine Parry
0646e08609 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6 All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
Kip Macsai-Goren
ba134eb166 partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields 2021-05-24 20:59:26 -04:00
James E. Stine
1704fdc877 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
Ross Thompson
3c5e87d6c2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Ross Thompson
daf344f1ba Updated branch predictor tests/benchmarks. 2021-05-24 11:13:33 -05:00
Katherine Parry
55f22979ca FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
bbracker
142b02b30a improved PLIC test organization 2021-05-21 15:13:02 -04:00
James E. Stine
49a4097d97 Minor testbench updates to rv64icfd 2021-05-21 09:41:21 -05:00
James E. Stine
47487a625f Update to testbench-imperase for rv64icfd 2021-05-21 09:28:44 -05:00
James E. Stine
694e21541b Update to FLD/FSD testbench 2021-05-21 09:26:55 -05:00
James E. Stine
474d479280 Update to rv64icfd wally-config to run through FP tests 2021-05-21 09:22:17 -05:00
Katherine Parry
67a41748ba FMV.D.X imperas test passes 2021-05-20 22:18:33 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
114bba8370 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
bbracker
fd4fae0406 commented out MSTATUS test 2021-05-19 12:38:01 -04:00
James E. Stine
f407bee5ae Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
David Harris
7dcc53dcf5 fixed rv64mmu makefile 2021-05-18 14:25:55 -04:00
Katherine Parry
409438bc95 floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
bbracker
86d55cd07a fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
69ef758e78 regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
James E. Stine
41da78e0b6 Mod Imperas Testbench for updated Div/Rem 2021-05-17 16:56:30 -05:00
Domenico Ottolia
1c884338b0 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
ushakya22
6274c8cb80 Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Domenico Ottolia
14becde792 Re-add medeleg tests to testbench 2021-05-04 14:42:20 -04:00
ushakya22
da352c81e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
66344f0604 Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Domenico Ottolia
2c39c0a6a5 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
7c2481bea6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
4db3780ebb Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
39135f221e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
1556cc5b9f Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
Domenico Ottolia
84911e6345 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
4f5ef65aeb Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
1f6db293fa Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
12d8ff617b Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
353d4e9238 Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
db4e447a25 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
c10d332c6e working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
0be6b81df9 finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7 updated pipeline tests 2021-05-03 22:07:36 -04:00
Elizabeth Hedenberg
08bfaeffe3 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06 coremark directory changes 2021-05-03 19:35:06 -04:00
David Harris
699a8f3ac3 Extended maximum signature length to 1M 2021-05-03 15:29:20 -04:00
bbracker
acd99be7f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 09:23:52 -04:00
Noah Boorstin
8d417558ae busybear: remove now unneeded hack for fixed CSR issue 2021-05-01 15:17:04 -04:00
Katherine Parry
9252d08b41 fpu imperas tests run 2021-05-01 02:18:01 +00:00
bbracker
0d62440f60 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359 rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Domenico Ottolia
830787e3e1 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Ross Thompson
893e03d55b Fixed memory size in configs for rv32ic and rv64ic. 
Removed warning on call to $fscanf.
 2021-04-29 17:36:46 -05:00
Domenico Ottolia
750d276feb Minor improvements to scause test 2021-04-29 16:48:07 -04:00
Domenico Ottolia
fdbd238a87 Add machine-mode timer interrupts to mcause tests 2021-04-29 16:39:18 -04:00
Domenico Ottolia
c9cb2f51d1 Same but don't break sim-wally this time 2021-04-29 15:33:27 -04:00
Domenico Ottolia
fdd4deec2f Add more exceptions to medeleg tests 2021-04-29 15:32:13 -04:00
ushakya22
f139f248dc Working MIE timer tests 2021-04-29 15:19:43 -04:00
Domenico Ottolia
99a927be47 Add medeleg tests 2021-04-29 15:02:36 -04:00
Noah Boorstin
9275f141f9 same but do that right this time 2021-04-28 14:27:28 -04:00
Noah Boorstin
fce3d6a8b1 busybear: respect branch predictor disable config 2021-04-27 15:52:18 -04:00
Ross Thompson
d191bc6cc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
922c8e450f ok but do that better 2021-04-26 14:38:05 -04:00
Noah Boorstin
24bbb674d3 linux: start using internal branch predictor signal 2021-04-26 14:34:38 -04:00
Noah Boorstin
9cbc769083 minor busybear fixes 2021-04-26 13:24:39 -04:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
f921886451 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
7947858481 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
8d77012995 progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
46a1616079 thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
dc3ffc9244 Add address translation to busybear testbench 2021-04-23 20:12:20 -04:00
Noah Boorstin
50df9d11e1 busybear 2021-04-23 17:32:37 -04:00
Shriya Nadgauda
2a5c243b0b adding pipeline testing 2021-04-23 14:19:17 -04:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Thomas Fleming
f9e071baf8 Temporarily disable rv64 mmu test 
Will restore once cache revamp is pushed
 2021-04-22 13:19:18 -04:00
Noah Boorstin
0afd5ae5f6 buildroot: add workaround for weird initial MSTATUS state 2021-04-21 16:03:42 -04:00
Domenico Ottolia
82320033d5 Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Noah Boorstin
c7a09d2359 yay buildroot passes a decent amount of tests now 
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
 2021-04-19 03:26:08 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Noah Boorstin
10c7ac7f73 slowly more buildroot progress 2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
5902637632 buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
8c4cfa5f69 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1 busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Noah Boorstin
5f1cd43033 try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
0a20e33971 Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Noah Boorstin
c820910b29 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Noah Boorstin
4e62c7d5f5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58 Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
a3925505bf fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
dd0b3fde59 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
335178a1d3 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
85164c7a87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
9f0a58e193 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
606295db2f Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1 Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
73d4dd8c15 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
9eb1786fb1 busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Domenico Ottolia
fb00d0f209 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
9cbdb44728 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
Teo Ene
1e691e120b Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
6a7b69ff2d Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Ross Thompson
a768c0406c Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
3909158619 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Ross Thompson
c7e34bd4a0 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
9909bdd4d5 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
e6aef66853 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
355961f834 busybear: more progress 2021-03-23 14:49:30 -04:00
Noah Boorstin
0dae5401f3 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
7fb2ebec50 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Noah Boorstin
3c131bb2bd start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
1592332d41 Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
43d23e3d9b busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0 busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
Jarred Allen
99fa8beef3 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
7350b9f18f busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
507d8ed120 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
c4fb51fad1 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
bab0e3b90f Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
e32291bcc2 Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
665c244ba1 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
804407eab7 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Teo Ene
0ff785549e Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e39ead0460 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
29634f1475 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
90946d61c5 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
ca901513c8 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
bccd37d778 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
a3b2ffb2c9 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
0e2352a6de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21 Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Noah Boorstin
45ed2742cf busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Domenico Ottolia
c9d70a1778 Add privileged testbench 2021-03-16 20:28:38 -04:00
Shreya Sanghai
a79e26f9d8 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
662ab53746 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
6d8bcfe6bf copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
8e51935082 Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Ross Thompson
0edaa625e3 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
David Harris
4465854423 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
d4e84c58ed 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
b1d1f3995c Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
f31d7a7f5c busybear: account for CSR moving 2021-03-11 06:45:14 +00:00
Jarred Allen
ff48a9e992 Return testbench to normal 2021-03-10 22:58:41 -05:00
Ross Thompson
f1f7884e10 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Ross Thompson
7b7cacbaf0 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
81b29a3891 More progress 2021-03-09 21:16:07 -05:00
David Harris
0baa004bb4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
87e2a9b920 busybear: better NOPing out of float instructions 2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2 busybear: better instrF checking 
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
 2021-03-08 19:48:12 +00:00
Noah Boorstin
1fc00d41c2 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
464c1de03d busybear: slight testbench update 2021-03-05 19:00:40 +00:00
Ross Thompson
7902c3fdb6 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Jarred Allen
5da98b5381 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Jarred Allen
b0f4d8e8d4 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Noah Boorstin
fde94f9057 Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00