mirror of
https://github.com/openhwgroup/cvw
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Add medeleg tests
This commit is contained in:
Domenico Ottolia
parent
246b41e604
commit
99a927be47
@ -30,34 +30,43 @@ vlib work
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined.do ../config/rv32ic
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switch $argc {
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0 {vlog +incdir+../config/rv64ic ../testbench/testbench-privileged.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 ../testbench/testbench-privileged.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
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0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
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}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench -o workopt
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vsim workopt
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view wave
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-- display input and output signals as hexidecimal values
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do ./wave-dos/default-waves.do
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-- Set Wave Output Items
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onerror {resume}
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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quietly WaveActivateNextPane {} 0
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TreeUpdate [SetDefaultTree]
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WaveRestoreZoom {0 ps} {100 ps}
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WaveRestoreCursors {{Cursor 2} {12215488 ns} 0} {{Cursor 4} {22127 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 140
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configure wave -valuecolwidth 513
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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set DefaultRadix hexadecimal
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {21993 ns} {22181 ns}
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-- Run the Simulation
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#run 4100
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#run 5000
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run -all
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#quit
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noview ../testbench/testbench-imperas.sv
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view wave
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@ -354,7 +354,8 @@ module testbench();
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"rv64p/WALLY-MARCHID", "4000",
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"rv64p/WALLY-MIMPID", "4000",
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"rv64p/WALLY-MHARTID", "4000",
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"rv64p/WALLY-MVENDORID", "4000"
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"rv64p/WALLY-MVENDORID", "4000",
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"rv64p/WALLY-MEDELEG", "2000"
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};
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string tests32p[] = '{
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@ -368,6 +369,7 @@ module testbench();
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"rv32p/WALLY-MIMPID", "4000",
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"rv32p/WALLY-MHARTID", "4000",
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"rv32p/WALLY-MVENDORID", "4000"
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//"rv32p/WALLY-MEDELEG", "2000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
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};
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string tests64periph[] = '{
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@ -61,6 +61,37 @@ def writeVectors(storecmd, returningInstruction):
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# Supervior timer interrupt: True, 5
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# Machine timer interrupt: True, 7
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# if fromMode == "m":
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# clintAddr = "0x2004000"
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# writeTest(storecmd, f, r, f"""
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# li x1, 0x8
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# csrrs x0, {fromMode}status, x1
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# la x18, {clintAddr}
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# lw x11, 0(x18)
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# li x1, 1
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# # {storecmd} x1, 0(x18)
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# li x1, 0x80
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# csrrs x0, {fromMode}ie, x1
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# nop
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# nop
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# nop
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# nop
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# nop
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# nop
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# nop
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# """, True, 4, f"""
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# li x1, 0x80
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# # csrrc x0, {fromMode}ie, x1
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# li x1, 0x8
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# # csrrc x0, {fromMode}status, x1
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# la x18, {clintAddr}
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# {storecmd} x11, 0(x18)
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# """)
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# writeTest(storecmd, f, r, f"""
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# li x10, MASK_XLEN(0x8)
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# csrrs x0, mstatus, x10
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@ -194,7 +225,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = "
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expected = code
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if(interrupt):
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expected+=(1 << (wordsize - 1))
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expected+=(1 << (xlen - 1))
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trapEnd = ""
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@ -316,6 +347,8 @@ for xlen in xlens:
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csrs sedeleg, x9
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"""
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clintAddr = "0x2004000"
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lines += f"""
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li x30, 0
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@ -328,6 +361,32 @@ for xlen in xlens:
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j _j_t_begin_{returningInstruction}
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_j_m_trap_{returningInstruction}:
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#li x1, 0x20
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#csrrw x0, mie, x1
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li x11, 0x3fffffffffffffff
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la x18, {clintAddr}
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{storecmd} x11, 0(x18)
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li x1, 0x8
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csrrc x0, mstatus, x1
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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csrrs x1, mepc, x0
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{"csrr x25, mcause" if testMode == "m" else "li x25, 0xBAD00003"}
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266
wally-pipelined/testgen/privileged/testgen-DELEG.py
Normal file
266
wally-pipelined/testgen/privileged/testgen-DELEG.py
Normal file
@ -0,0 +1,266 @@
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#!/usr/bin/python3
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##################################
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# testgen-CAUSE.py
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#
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# dottolia@hmc.edu 27 Apr 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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#
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#
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##################################
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# DOCUMENTATION:
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# Most of the comments explaining what everything
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# does can be found in testgen-TVAL.py
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###################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# functions
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##################################
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#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
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def randRegs():
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reg1 = randint(1,20)
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reg2 = randint(1,20)
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reg3 = randint(1,20)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return str(reg1), str(reg2), str(reg3)
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def writeVectors(storecmd):
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global testnum
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# User Software Interrupt: True, 0
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# Supervisor Software Interrupt: True, 1
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# Machine Software Interrupt: True, 2
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# User external input: True, 8
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# Supervisor external input: True, 9
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# Machine externa input: True, 11
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# Instruction address misaligned: False, 0
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# Instruction access fault: False, 1
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# Illegal Instruction
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#writeTest(storecmd, f, r, "ecall", False, 11, "m")
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# Breakpoint
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writeTest(storecmd, f, r, "ebreak", False, 3)
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# Load Address Misaligned
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# writeTest(storecmd, f, r, f"""
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# lw x0, 11(x0)
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# """, False, 4)
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# # Load Access fault: False, 5
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# # Store/AMO address misaligned
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# writeTest(storecmd, f, r, f"""
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# sw x0, 11(x0)
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# """, False, 6)
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#writeTest(storecmd, f, r, "ecall", False, 11, "m")
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def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = ""):
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global testnum
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global testMode
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global isInterrupts
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if interrupt != isInterrupts:
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return
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mask = 1 << code
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delegateType = "i" if interrupt else "e"
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for mode in (["m", "s", "u"] if testMode == "m" else ["s", "u"]):
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for delegated in [True, False]:
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labelSuffix = testnum
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f.write(f"""
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_start_{labelSuffix}:
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la x1, _j_m_trap_{labelSuffix}
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csrw mtvec, x1
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la x1, _j_s_trap_{labelSuffix}
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csrw stvec, x1
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j _j_test_{labelSuffix}
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_j_m_trap_{labelSuffix}:
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li x25, 3
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csrr x1, mepc
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addi x1, x1, 4
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csrrw x0, mepc, x1
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bnez x30, _j_finished_{labelSuffix}
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mret
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_j_s_trap_{labelSuffix}:
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li x25, 1
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csrr x1, sepc
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addi x1, x1, 4
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csrrw x0, sepc, x1
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bnez x30, _j_goto_machine_mode_{labelSuffix}
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sret
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_j_goto_machine_mode_{labelSuffix}:
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li x30, 1
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{"ebreak" if test is not "ebreak" else "ecall"}
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_j_test_{labelSuffix}:
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""")
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original = f"""
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li x1, {mask if delegated else 0}
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csrw m{delegateType}deleg, x1
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"""
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lines = original + "\n" + test
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if mode != "m":
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lines = f"""
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{original}
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li x1, 0b110000000000
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csrrc x28, {testMode}status, x1
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li x1, 0b{"01" if mode == "s" else "00"}00000000000
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csrrs x28, {testMode}status, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the ret instruction
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csrrw x27, {testMode}epc, x1
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{testMode}ret
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# From {testMode}, we're now in {mode} mode...
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{test}
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"""
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writeTestInner(storecmd, f, r, lines, 1 if delegated else 3)
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f.write(f"""
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j _j_goto_machine_mode_{labelSuffix}
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""")
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else:
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writeTestInner(storecmd, f, r, lines, 3)
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f.write(f"""
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_j_finished_{labelSuffix}:
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li x30, 0
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""")
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def writeTestInner(storecmd, f, r, lines, expected):
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global testnum
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lines = f"""
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li x25, 0xDEADBEA7
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{lines}
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"""
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lines += storecmd + " x25, " + str(testnum * wordsize) + "(x6)\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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##################################
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# main body
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##################################
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# change these to suite your tests
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 1;
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# setup
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seed(0xD0C0_D0C0_D0C0_D0C0) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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for testMode in ["m"]:
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for isInterrupts in [True, False]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-" + testMode.upper() + ("I" if isInterrupts else "E") + "DELEG"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# All registers used:
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: mideleg old value
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f.write(f"""
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add x7, x6, x0
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csrr x19, mtvec
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csrr x18, medeleg
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csrr x17, medeleg
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""")
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print("\n\n" + basename)
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testnum = 0
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for i in range(0, 2):
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writeVectors(storecmd)
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print(testnum)
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f.write(f"""
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csrw mtvec, x19
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csrw medeleg, x18
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csrw mideleg, x17
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""")
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# if we're in supervisor mode, this leaves the ebreak instruction untested (we need a way to)
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# get back to machine mode.
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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@ -1,6 +1,6 @@
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#!/usr/bin/python3
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##################################
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# testgen-CAUSE.py (new)
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# testgen-TVEC.py (new)
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#
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# dottolia@hmc.edu 1 Mar 2021
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#
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@ -25,6 +25,12 @@ from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# setup
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##################################
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areVectoredTrapsSupported = True
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##################################
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# functions
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##################################
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@ -43,29 +49,6 @@ def randRegs():
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def writeVectors(storecmd, returningInstruction):
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global testnum
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if fromMode == "m":
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expectedCode = 7 if fromMode == "m" else 5
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clintAddr = "0x2004000"
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writeTest(storecmd, f, r, f"""
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li x1, 0x8
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csrrs x0, {fromMode}status, x1
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la x18, {clintAddr}
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lw x11, 0(x18)
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li x1, 1
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{storecmd} x1, 0(x18)
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li x1, 0x80
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csrrs x0, {fromMode}ie, x1
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""", True, expectedCode, f"""
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la x18, {clintAddr}
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{storecmd} x11, 0(x18)
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li x1, 0x80
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csrrc x0, {fromMode}ie, x1
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""")
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# Illegal Instruction
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writeTest(storecmd, f, r, f"""
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@ -112,6 +95,35 @@ def writeVectors(storecmd, returningInstruction):
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ecall
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""", False, 0)
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if fromMode == "m":
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expectedCode = 7 if fromMode == "m" else 5
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clintAddr = "0x2004000"
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||||
writeTest(storecmd, f, r, f"""
|
||||
li x1, 0x8
|
||||
csrrs x0, {fromMode}status, x1
|
||||
|
||||
la x18, {clintAddr}
|
||||
lw x11, 0(x18)
|
||||
li x1, 0x3fffffffffffffff
|
||||
{storecmd} x1, 0(x18)
|
||||
|
||||
li x1, 0x80
|
||||
csrrs x0, {fromMode}ie, x1
|
||||
|
||||
{storecmd} x0, 0(x18)
|
||||
""", True, expectedCode, f"""
|
||||
li x1, 0x80
|
||||
csrrc x0, {fromMode}ie, x1
|
||||
|
||||
li x1, 0x8
|
||||
csrrc x0, {fromMode}status, x1
|
||||
|
||||
la x18, {clintAddr}
|
||||
{storecmd} x0, 0(x18)
|
||||
""")
|
||||
|
||||
# Instruction page fault: 12
|
||||
# Load page fault: 13
|
||||
# Store/AMO page fault: 15
|
||||
@ -144,14 +156,13 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
|
||||
{test}
|
||||
"""
|
||||
|
||||
# We expect x25 to be 0 always. This is because of the code we wrote at the begining
|
||||
# of this function
|
||||
|
||||
# Store the expected value of x25 to memory and in the .reference_output file
|
||||
lines += f"""
|
||||
{storecmd} x25, {testnum * wordsize}(x6)
|
||||
"""
|
||||
|
||||
if not areVectoredTrapsSupported:
|
||||
expected = 0
|
||||
|
||||
f.write(lines)
|
||||
if (xlen == 32):
|
||||
line = formatrefstr.format(expected)+"\n"
|
||||
@ -291,7 +302,7 @@ for xlen in xlens:
|
||||
|
||||
# Set up
|
||||
la x1, _j_m_trap_{returningInstruction}
|
||||
addi x1, 1
|
||||
#addi x1, 1
|
||||
csrw mtvec, x1
|
||||
la x1, _j_s_trap_{returningInstruction}
|
||||
csrw stvec, x1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user