ushakya22 f139f248dc Working MIE timer tests		2021-04-29 15:19:43 -04:00
..
function_radix.sv	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
testbench-busybear.sv	same but do that right this time	2021-04-28 14:27:28 -04:00
testbench-coremark_bare.sv	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
testbench-coremark.sv	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
testbench-imperas.sv	Working MIE timer tests	2021-04-29 15:19:43 -04:00
testbench-privileged.sv	Remove imem from testbenches	2021-04-14 20:20:34 -04:00