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https://github.com/openhwgroup/cvw
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18a4d5fc8d
start speculative checking on CSR* satp, * add some slight delays in some CSR checkings to make them deterministic I realize this verilog is incredibly un-idiomatic. But I still don't know of anything better. If you figure it out, please let me know |
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function_radix.sv | ||
testbench-busybear.sv | ||
testbench-coremark_bare.sv | ||
testbench-coremark.sv | ||
testbench-imperas.sv | ||
testbench-peripherals.sv | ||
testbench-privileged.sv |