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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Add mtvec and stvec tests to testbench
This commit is contained in:
Domenico Ottolia
parent
c10d332c6e
commit
db4e447a25
@ -354,6 +354,8 @@ module testbench();
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"rv64p/WALLY-SEPC", "4000",
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"rv64p/WALLY-MTVAL", "6000",
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"rv64p/WALLY-STVAL", "4000",
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"rv64p/WALLY-MTVEC", "2000",
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"rv64p/WALLY-STVEC", "2000",
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"rv64p/WALLY-MARCHID", "4000",
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"rv64p/WALLY-MIMPID", "4000",
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"rv64p/WALLY-MHARTID", "4000",
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@ -371,6 +373,8 @@ module testbench();
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// "rv32p/WALLY-MIMPID", "4000",
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// "rv32p/WALLY-MHARTID", "4000",
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// "rv32p/WALLY-MVENDORID", "4000"
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// "rv32p/WALLY-MTVEC", "2000",
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// "rv32p/WALLY-STVEC", "2000"
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};
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string tests64periph[] = '{
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@ -190,7 +190,9 @@ for xlen in xlens:
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# This is the address we write results to
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# x6: Starting address we should write expected results to
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# ...
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# x1 - x5 can be freely written
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# x4 & x5 can be freely written
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# x3 — DO NOT WRITE ANY NON-ZERO VALUE TO THIS — test exits on ecall if x3 = 1 (x3 is gp)
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# x1 & x2 can be freely written
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@ -51,52 +51,39 @@ def writeVectors(storecmd, returningInstruction):
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# Illegal Instruction
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writeTest(storecmd, f, r, f"""
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.fill 1, 4, 0
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""", False, 0)
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# writeTest(storecmd, f, r, f"""
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# .fill 1, 4, 0
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# """, False, 0)
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# Breakpoint
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if returningInstruction != "ebreak":
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# # Breakpoint
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# if returningInstruction != "ebreak":
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# writeTest(storecmd, f, r, f"""
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# ebreak
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# """, False, 0)
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# # Load Address Misaligned
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# writeTest(storecmd, f, r, f"""
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# lw x0, 11(x0)
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# """, False, 0)
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# # Load Access fault: False, 5
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# # Store/AMO address misaligned
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# writeTest(storecmd, f, r, f"""
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# sw x0, 11(x0)
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# """, False, 0)
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# # Environment call from u-mode: only for when only M and U mode enabled?
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# # writeTest(storecmd, f, r, f"""
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# # ecall
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# # """, False, 8, "u")
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if returningInstruction != "ecall":
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writeTest(storecmd, f, r, f"""
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ebreak
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ecall
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""", False, 0)
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# Load Address Misaligned
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writeTest(storecmd, f, r, f"""
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lw x0, 11(x0)
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""", False, 0)
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# Load Access fault: False, 5
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# Store/AMO address misaligned
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writeTest(storecmd, f, r, f"""
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sw x0, 11(x0)
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""", False, 0)
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# Environment call from u-mode: only for when only M and U mode enabled?
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# writeTest(storecmd, f, r, f"""
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# ecall
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# """, False, 8, "u")
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if returningInstruction != "ecall":
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if fromMode == "u":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 0)
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# Environment call from s-mode
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if fromMode == "s":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 0)
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# Environment call from m-mode
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if fromMode == "m":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 0)
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if fromMode == "m":
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if fromMode == "m" and testMode == "m":
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expectedCode = 7 if fromMode == "m" else 5
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clintAddr = "0x2004000"
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@ -105,9 +92,9 @@ def writeVectors(storecmd, returningInstruction):
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csrrs x0, {fromMode}status, x1
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la x18, {clintAddr}
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lw x11, 0(x18)
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li x1, 0x3fffffffffffffff
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{storecmd} x1, 0(x18)
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# lw x11, 0(x18)
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# li x1, 0x3fffffffffffffff
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# {storecmd} x1, 0(x18)
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li x1, 0x80
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csrrs x0, {fromMode}ie, x1
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@ -132,7 +119,7 @@ def writeVectors(storecmd, returningInstruction):
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def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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global testnum, storeAddressOffset
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global testnum, storeAddressOffset, xlen
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expected = code
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@ -156,19 +143,27 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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{test}
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"""
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lines += f"""
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if not areVectoredTrapsSupported or not vectoredInterrupts:
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expected = 0
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writeGeneralTest(storecmd, f, r, lines, expected)
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def writeGeneralTest(storecmd, f, r, test, expected):
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global testnum, storeAddressOffset, xlen
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lines = f"""
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{test}
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{storecmd} x25, {testnum * wordsize}(x6)
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"""
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if not areVectoredTrapsSupported:
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expected = 0
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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##################################
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@ -177,7 +172,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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testCount = 16;
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testCount = 4;
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# setup
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# Change this seed to a different constant value for every test
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@ -219,6 +214,25 @@ for xlen in xlens:
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for line in h:
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f.write(line)
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# Ensure MODE of *tvec (last 2 bits) is either 00 or 01
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f.write(f"""
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csrr x19, {testMode}tvec
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""")
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for i in range(0, 16):
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i = i;
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trySet = i | 0b10;
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expected = trySet & 0xFFFF_FFFFD;
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writeGeneralTest(storecmd, f, r, f"""
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li x1, {trySet}
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csrw {testMode}tvec, x1
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csrr x25, {testMode}tvec
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""", expected)
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f.write(f"""
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csrw {testMode}tvec, x19
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""")
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# We need to leave at least one bit in medeleg unset so that we have a way to get
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# back to machine mode when the tests are complete (otherwise we'll only ever be able
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# to get up to supervisor mode).
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@ -233,211 +247,218 @@ for xlen in xlens:
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# For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
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# returning instruction. For others, like testgen-CAUSE, we'll need to put
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# both ebreak and ecall here.
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for returningInstruction in ["ebreak"]:
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for vectoredInterrupts in [True, False]:
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# All registers used:
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# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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# ...
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# x28: address trap handler should jump to for the test
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# x27: address the test should return to after the test
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# ...
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# x25: value to write to memory
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# ...
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# x20: intermediate value in trap handler. Don't overwrite this!
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: sedeleg old value (currently unused — user mode traps deprecated)
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# x16: mideleg old value
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# ...
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# x10 - x14 can be freely written
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# ...
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# x7: copy of x6. Increment this instead of using an offset on x6.
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# this allows us to create more than 2048/wordlen tests.
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# This is the address we write results to
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# x6: Starting address we should write expected results to
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# ...
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# x1 - x5 can be freely written
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# All registers used:
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# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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# ...
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# x28: address trap handler should jump to for the test
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# x27: address the test should return to after the test
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# ...
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# x25: value to write to memory
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# ...
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# x20: intermediate value in trap handler. Don't overwrite this!
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: sedeleg old value (currently unused — user mode traps deprecated)
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# x16: mideleg old value
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# ...
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# x10 - x14 can be freely written
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# ...
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# x7: copy of x6. Increment this instead of using an offset on x6.
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# this allows us to create more than 2048/wordlen tests.
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# This is the address we write results to
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# x6: Starting address we should write expected results to
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# ...
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# x1 - x5 can be freely written
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# Set up x7 and store old value of mtvec
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lines = f"""
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add x7, x6, x0
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csrr x19, mtvec
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"""
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# Not used — user mode traps are deprecated
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if testMode == "u":
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lines += f"""
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csrr x17, sedeleg
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li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
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csrs sedeleg, x9
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"""
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# Code that will jump to the test (x28 is set in writeTest above)
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testJumpCode = f"""
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auipc x27, 0
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addi x27, x27, 12
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jr x28
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"""
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beforeCode = ""
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for i in range(0, 16):
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beforeCode+=f"""
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nop
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nop
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li x25, {i}
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j _j_m_trap_end_{returningInstruction}
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# Set up x7 and store old value of mtvec
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lines = f"""
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# add x7, x6, x0
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csrr x19, mtvec
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"""
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########
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####### FIXME: wally is causing exception code 1 when you put non 4-bit aligned into mtvec. Bad wally.
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########
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# Code for handling traps in different modes
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# Some comments are inside of the below strings (prefixed with a #, as you might expected)
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lines += f"""
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# Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
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li x30, 0
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# Set up
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la x1, _j_m_trap_{returningInstruction}
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#addi x1, 1
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csrw mtvec, x1
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la x1, _j_s_trap_{returningInstruction}
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csrw stvec, x1
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la x1, _j_u_trap_{returningInstruction}
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# csrw utvec, x1 # user mode traps are not supported
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# Start the tests!
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j _j_t_begin_{returningInstruction}
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# Machine mode traps
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_j_m_trap_{returningInstruction}:
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{beforeCode}
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_j_m_trap_end_{returningInstruction}:
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{testJumpCode}
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csrrs x20, mepc, x0
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addi x20, x20, 4
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csrrw x0, mepc, x20
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bnez x30, _j_all_end_{returningInstruction}
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mret
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# Supervisor mode traps
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_j_s_trap_{returningInstruction}:
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{testJumpCode if testMode == "s" else "li x25, 0xBAD00001"}
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csrrs x20, sepc, x0
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addi x20, x20, 4
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csrrw x0, sepc, x20
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bnez x30, _j_goto_machine_mode_{returningInstruction}
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sret
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# Unused: user mode traps are no longer supported
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_j_u_trap_{returningInstruction}:
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{testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
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csrrs x20, uepc, x0
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addi x20, x20, 4
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csrrw x0, uepc, x20
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bnez x30, _j_goto_supervisor_mode_{returningInstruction}
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uret
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# Currently unused. Just jumps to _j_goto_machine_mode. If you actually
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# want to implement this, you'll likely need to reset sedeleg here
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# and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
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_j_goto_supervisor_mode_{returningInstruction}:
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j _j_goto_machine_mode_{returningInstruction}
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_j_goto_machine_mode_{returningInstruction}:
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li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking...
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{returningInstruction} # ... this instruction!
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# Run the actual tests!
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_j_t_begin_{returningInstruction}:
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"""
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fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
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# We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
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# back to machine mode at the end! (and we need to be in machine mode to complete the tests)
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medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
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# Set medeleg and mideleg
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lines += f"""
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csrr x18, medeleg
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li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
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csrw medeleg, x9
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csrr x16, mideleg
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li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
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csrw mideleg, x9
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"""
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f.write(lines)
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for fromMode in fromModeOptions:
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lines = ""
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# Code to bring us down to supervisor mode
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if fromMode == "s" or fromMode == "u":
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# Not used — user mode traps are deprecated
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if testMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b0100000000000
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csrrs x28, mstatus, x1
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csrr x17, sedeleg
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li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
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csrs sedeleg, x9
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"""
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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# Code that will jump to the test (x28 is set in writeTest above)
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testJumpCode = f"""
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auipc x27, 0
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addi x27, x27, 12
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jr x28
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"""
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# We're now in supervisor mode...
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"""
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beforeCode = {"m": "", "s": ""}
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for pm in ["m", "s"]:
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for i in range(0, 16):
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beforeCode[pm] = beforeCode[pm] + f"""
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nop
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nop
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li x25, {i}
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j _j_{pm}_trap_end_{returningInstruction}_{vectoredInterrupts}
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"""
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# Code to bring us down to user mode
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if fromMode == "u":
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lines += f"""
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# Code for handling traps in different modes
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# Some comments are inside of the below strings (prefixed with a #, as you might expected)
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enableVectored = "addi x1, x1, 1" if vectoredInterrupts else ""
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li x1, 0b110000000000
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csrrc x28, sstatus, x1
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lines += f"""
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# Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
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li x30, 0
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the sret instruction
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csrw sepc, x1
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# Set up
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la x1, _j_m_trap_{returningInstruction}_{vectoredInterrupts}
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{enableVectored} # enable/don't enable vectored interrupts
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csrw mtvec, x1
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la x1, _j_s_trap_{returningInstruction}_{vectoredInterrupts}
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{enableVectored} # enable/don't enable vectored interrupts
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csrw stvec, x1
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la x1, _j_u_trap_{returningInstruction}_{vectoredInterrupts}
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{enableVectored} # enable/don't enable vectored interrupts
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# csrw utvec, x1 # user mode traps are not supported
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# Start the tests!
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j _j_t_begin_{returningInstruction}_{vectoredInterrupts}
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# Machine mode traps
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_j_m_trap_{returningInstruction}_{vectoredInterrupts}:
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{beforeCode['m']}
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_j_m_trap_end_{returningInstruction}_{vectoredInterrupts}:
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{testJumpCode}
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csrrs x20, mepc, x0
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addi x20, x20, 4
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csrrw x0, mepc, x20
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bnez x30, _j_all_end_{returningInstruction}_{vectoredInterrupts}
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mret
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# Supervisor mode traps
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_j_s_trap_{returningInstruction}_{vectoredInterrupts}:
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{beforeCode['s']}
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_j_s_trap_end_{returningInstruction}_{vectoredInterrupts}:
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{testJumpCode}
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||||
|
||||
csrrs x20, sepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, sepc, x20
|
||||
bnez x30, _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
|
||||
sret
|
||||
|
||||
# We're now in user mode...
|
||||
"""
|
||||
# Unused: user mode traps are no longer supported
|
||||
_j_u_trap_{returningInstruction}_{vectoredInterrupts}:
|
||||
{testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
|
||||
|
||||
csrrs x20, uepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, uepc, x20
|
||||
bnez x30, _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}
|
||||
uret
|
||||
|
||||
# Currently unused. Just jumps to _j_goto_machine_mode. If you actually
|
||||
# want to implement this, you'll likely need to reset sedeleg here
|
||||
# and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
|
||||
_j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}:
|
||||
j _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
|
||||
|
||||
_j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}:
|
||||
li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction}_{vectoredInterrupts} in the machine trap handler, which we'll get into by invoking...
|
||||
{returningInstruction} # ... this instruction!
|
||||
|
||||
# Run the actual tests!
|
||||
_j_t_begin_{returningInstruction}_{vectoredInterrupts}:
|
||||
"""
|
||||
|
||||
fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
|
||||
|
||||
# We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
|
||||
# back to machine mode at the end! (and we need to be in machine mode to complete the tests)
|
||||
medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
|
||||
|
||||
# Set medeleg and mideleg
|
||||
lines += f"""
|
||||
csrr x18, medeleg
|
||||
li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw medeleg, x9
|
||||
|
||||
csrr x16, mideleg
|
||||
li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw mideleg, x9
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
for i in range(0,testCount):
|
||||
writeVectors(storecmd, returningInstruction)
|
||||
|
||||
for fromMode in fromModeOptions:
|
||||
lines = ""
|
||||
|
||||
# Code to bring us down to supervisor mode
|
||||
if fromMode == "s" or fromMode == "u":
|
||||
lines += f"""
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, mstatus, x1
|
||||
li x1, 0b0100000000000
|
||||
csrrs x28, mstatus, x1
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the mret instruction
|
||||
csrw mepc, x1
|
||||
mret
|
||||
|
||||
# We're now in supervisor mode...
|
||||
"""
|
||||
|
||||
# Code to bring us down to user mode
|
||||
if fromMode == "u":
|
||||
lines += f"""
|
||||
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, sstatus, x1
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the sret instruction
|
||||
csrw sepc, x1
|
||||
sret
|
||||
|
||||
# We're now in user mode...
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
for i in range(0,testCount):
|
||||
writeVectors(storecmd, returningInstruction)
|
||||
|
||||
|
||||
# Very end of test. Bring us back up to machine mode
|
||||
# We set x30 to 1, which will cause us to branch to _j_all_end in the
|
||||
# machine mode trap handler, before executing the mret instruction. This will
|
||||
# make us stay in machine mode.
|
||||
#
|
||||
# If we're currently in user mode, this will first bump us up to the supervisor mode
|
||||
# trap handler, which will call returningInstruction again before it's sret instruction,
|
||||
# bumping us up to machine mode
|
||||
#
|
||||
# Get into the trap handler by running returningInstruction (either an ecall or ebreak)
|
||||
f.write(f"""
|
||||
li x30, 1
|
||||
li gp, 0
|
||||
{returningInstruction}
|
||||
_j_all_end_{returningInstruction}:
|
||||
# Very end of test. Bring us back up to machine mode
|
||||
# We set x30 to 1, which will cause us to branch to _j_all_end in the
|
||||
# machine mode trap handler, before executing the mret instruction. This will
|
||||
# make us stay in machine mode.
|
||||
#
|
||||
# If we're currently in user mode, this will first bump us up to the supervisor mode
|
||||
# trap handler, which will call returningInstruction again before it's sret instruction,
|
||||
# bumping us up to machine mode
|
||||
#
|
||||
# Get into the trap handler by running returningInstruction (either an ecall or ebreak)
|
||||
f.write(f"""
|
||||
li x30, 1
|
||||
li gp, 0
|
||||
{returningInstruction}
|
||||
_j_all_end_{returningInstruction}_{vectoredInterrupts}:
|
||||
|
||||
# Reset trap handling csrs to old values
|
||||
csrw mtvec, x19
|
||||
csrw medeleg, x18
|
||||
csrw mideleg, x16
|
||||
""")
|
||||
# Reset trap handling csrs to old values
|
||||
csrw mtvec, x19
|
||||
csrw medeleg, x18
|
||||
csrw mideleg, x16
|
||||
""")
|
||||
|
||||
# print footer
|
||||
h = open("../testgen_footer.S", "r")
|
||||
@ -450,8 +471,3 @@ for xlen in xlens:
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user