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668 Commits

Author SHA1 Message Date
David Harris
b4c9998b26 Increased timeout for riscof because it is so slow 2023-05-23 15:37:09 -07:00
David Harris
19096a812a Added Zifencei ISA to tests where necessary to support new compiler 2023-05-16 11:18:27 -07:00
David Harris
0a7a159d69 Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile 2023-05-14 06:58:29 -07:00
David Harris
0cc8f9fd15 Fixed riscof scripts that were removing zicsr from compiler misa 2023-05-14 04:19:08 -07:00
David Harris
67a089104c Defined empty RVMODEL interrupt macros to make riscof warnings go away 2023-05-14 03:36:28 -07:00
Kevin Thomas
0c9b7dcce7 Comment tlbGBL more discriptively 
Reduce redundant instructions
 2023-05-04 19:13:47 -05:00
David Harris
ec3518673e Merge branch 'main' into main 2023-04-28 07:51:32 -07:00
Liam Chalk
028d19bbfa Merge branch 'main' into main 2023-04-27 21:49:01 -07:00
Kevin Wan
39c9cd5ee9 added tests for pmppriority module 2023-04-27 16:12:43 -07:00
David Harris
15fb5fa2ac Update tlbASID.S 
fixed comment about restoring ASID to 0
 2023-04-27 14:32:57 -07:00
Noah Limpert
4ec31de316 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Liam
4d8eafd27d Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
Alexa Wright
09095422d0 Merge branch 'openhwgroup:main' into main 2023-04-26 16:26:30 -07:00
Alexa Wright
59d913949f Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00
Liam
7bf2ee5418 pmpaddr0 and pmpaddr2 test cases 
Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
 2023-04-25 15:37:04 -07:00
David Harris
086556310c Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
Liam
c2f441724b pmpcfg test cases 
Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
 2023-04-21 20:43:37 -07:00
Noah Limpert
a0e71c26cb Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126 Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
Liam
4f57dca0dc Add pmpcfg test cases increasing IFU coverage 2023-04-19 11:58:22 -07:00
David Harris
4cbffd7972 Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
b63dff098a Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
Alec Vercruysse
b3a3af8ed3 add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
d74768ce04 Add test cases for pmpcfg.S 2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d a 2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a Merge branch 'main' of https://github.com/koooo142857/cvw into main 2023-04-18 21:55:06 -07:00
koooo142857
c9018b8204 Merge branch 'openhwgroup:main' into main 2023-04-18 21:53:46 -07:00
Kevin Wan
771124e265 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Miles Cook
5e45fef838 Increase of TLB coverage in IFU 2023-04-17 18:35:03 -07:00
Diego Herrera Vicioso
16fd17be39 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Dygore
cac9c2dc37 Added multiple tests to increase FPU coverage 2023-04-14 14:41:05 -05:00
Dylan
d7936a9214 Merge branch 'openhwgroup:main' into main 2023-04-14 00:36:57 -05:00
Dygore
69b4751162 Added tests for full coverage of the FPU result sign module 2023-04-14 00:36:12 -05:00
Noah Limpert
6a23bbea9d add back K. Box and M. Cook Lsu test 2023-04-13 17:50:18 -07:00
Noah Limpert
3683139637 make pull request more clean 2023-04-13 17:44:09 -07:00
Noah Limpert
b35d5bdbdb Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways" 
This reverts commit 6acf1dadda.
 2023-04-13 17:40:39 -07:00
Noah Limpert
d012715a60 Revert "Test File for Pull Request, Attempt to fill all four ways" 
This reverts commit e887341c80.
 2023-04-13 17:28:37 -07:00
Noah Limpert
034dabee54 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-13 17:00:48 -07:00
Noah Limpert
a0a9d35d19 update tests.vh, add tlbKP to load all lines of tlb 2023-04-13 15:13:55 -07:00
Dygore
4854e09124 Added a test for denormalized FP numbers 2023-04-13 16:39:27 -05:00
Noah Limpert
276ce87582 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 
pull in changes to trap handler so that permissions should change correctly
 2023-04-13 12:34:27 -07:00
Alexa Wright
23d0d45bf6 Fixed exception handling to handle ecalls properly 2023-04-13 09:23:32 -07:00
Kip Macsai-Goren
34200e8c76 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02 renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
b2d6084eea removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
a82c0a7780 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
e0b938b409 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
a899606c2b Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
19305fe60a Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
Noah Limpert
748c8dc234 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-10 19:01:32 -07:00
David Harris
90c9f29beb Merge pull request #226 from SydRiley/main 
Increased coverage for the fpu by adding directed tests to toggle signals
 2023-04-09 21:52:11 -07:00
Kevin Box
59e7c9371a Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
Noah Limpert
41c79303c6 3rd attempt to resolve conflict in lsu.S file 2023-04-09 15:52:18 -07:00
Sydeny
f4caa62efc Increasing coverage for the fpu by adding directed tests to toggle signals 2023-04-09 13:33:12 -07:00
Diego Herrera Vicioso
5f9c443781 Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs. 2023-04-08 16:40:36 -07:00
David Harris
b27199e276 Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
David Harris
0d2de13990 Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf 2023-04-07 21:11:01 -07:00
David Harris
bf9db11a57 Fixed priv.S to initialize stimecmp and agree with ImperasDV 2023-04-07 20:44:01 -07:00
David Harris
16eca598ba Fixed WALLY-init-lib to return correctly even from traps from compressed instructions 2023-04-07 20:24:33 -07:00
David Harris
a49f1f785e Fixed enabling machine timer interrupt 2023-04-06 22:18:33 -07:00
David Harris
8ef9891e46 vm64 tests 2023-04-06 21:42:47 -07:00
Jacob Pease
b796b1b492 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
David Harris
02053c5dc6 Merge pull request #210 from SydRiley/main 
Starting to extend fpu conditional coverage, reformatting ifu test cases.
 2023-04-05 14:56:16 -07:00
Sydeny
9e3d78de8b Starting to extend fpu conditional coverage, reformating ifu test cases 2023-04-05 14:10:15 -07:00
David Harris
32c5a1d83e Merge pull request #205 from kbox13/my-single-change 
Increase LSU Coverage
 2023-04-05 13:16:04 -07:00
Limnanthes Serafini
590f95d353 *.out removal 2023-04-05 12:50:26 -07:00
Limnanthes Serafini
baa537c5d3 *.out removal 2023-04-05 12:50:10 -07:00
Limnanthes Serafini
ecc580a140 *.out removal 2023-04-05 12:49:57 -07:00
Kevin Box
0f13148215 Add sfence.vma 2023-04-05 10:34:30 -07:00
Kevin Box
333bb87b05 Revert "Add sfence.vma and arch64d/f tests to increase coverage in the LSU" 
This reverts commit 28a9faa265.
 2023-04-05 10:32:25 -07:00
Kevin Box
28a9faa265 Add sfence.vma and arch64d/f tests to increase coverage in the LSU 2023-04-05 10:18:41 -07:00
Limnanthes Serafini
6ad5d81980 Further comments and attribution. 2023-04-05 02:46:31 -07:00
Limnanthes Serafini
0aadbd8492 Outfiles for the failing tests. 2023-04-05 02:42:09 -07:00
Limnanthes Serafini
6f7620e7c1 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Noah Limpert
6bcd47db99 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-04 20:22:00 -07:00
Noah Limpert
e887341c80 Test File for Pull Request, Attempt to fill all four ways 2023-04-03 21:54:27 -07:00
David Harris
64679654ff Merged priv.S edits 2023-04-03 18:07:14 -07:00
David Harris
fecdd6d139 Merge pull request #190 from SydRiley/main 
expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions
 2023-04-03 17:48:47 -07:00
Alexa Wright
c170777d63 Merge branch 'openhwgroup:main' into main 2023-04-03 14:30:54 -07:00
David Harris
4e2d80476e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
Sydeny
981e5bd5f6 Manual merge for fctrl.sv, fpu.S, and ifu.S files 2023-04-03 01:55:23 -07:00
Sydeny
17d41b4d52 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 01:54:27 -07:00
Sydney Riley
55655157ae expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
David Harris
5712b905a7 Merge pull request #177 from amaiuolo/main 
Integrated tv generation for IFdivsqrt
 2023-04-02 18:29:38 -07:00
Alexa Wright
59596cd7cc Added tests for writing and reading to HPMCOUNTERM csrs 2023-04-01 16:02:23 -07:00
David Harris
60a8a26f2e regression cleanup; unable to run buildroot coverage because of different config file 2023-03-31 09:59:38 -07:00
David Harris
fa17487d67 Merged privileged test 2023-03-31 08:37:16 -07:00
David Harris
db542543cb Coverage improvement: ieu, hazard, priv 2023-03-31 08:34:34 -07:00
David Harris
ab82bb397c Privilege test improvements 2023-03-31 08:32:02 -07:00
Marcus Mellor
219176db9b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 09:54:02 -05:00
Marcus Mellor
09b2cd304f Address comments in openhwgroup/cvw#180 2023-03-31 09:51:33 -05:00
Diego Herrera Vicioso
e711948369 Merge branch 'openhwgroup:main' into main 2023-03-31 00:35:02 -07:00
Marcus Mellor
d4cb1a8582 Add comments to fpu.S indicating which lines of src/fpu/fctrl.sv are covered 2023-03-30 20:01:11 -05:00
Alessandro Maiuolo
9b290669d5 integrated tv generation for IFdivsqrt 2023-03-29 20:57:26 -07:00
Kip Macsai-Goren
cfb236dd13 Merge branch 'priv-tests' of github.com:kipmacsaigoren/cvw into priv-tests 2023-03-29 16:31:35 -07:00
Kip Macsai-Goren
a7c9d3d37b ported medelg fixes to 32 bit tests. Requires a make allclean 2023-03-29 16:31:28 -07:00
kipmacsaigoren
5cc1bc97da Merge branch 'openhwgroup:main' into priv-tests 2023-03-29 15:34:47 -07:00
Sydney Riley
4bd3121364 Manual merge in the coverage64gc 2023-03-29 15:25:27 -07:00
Kip Macsai-Goren
2e151b6b08 updated tests to reflect non-writeable bits of deleg 2023-03-29 15:24:00 -07:00
Sydney Riley
20fec0177d Corrected authorship for IFU.S tests file 2023-03-29 15:20:46 -07:00
Sydney Riley
b0237eaa8b Starting IFU tests including c.fld compressed instruction 2023-03-29 15:15:47 -07:00
Noah Limpert
6acf1dadda instantiate 5 4KiB arrays, aim to thrash all 4 ways 2023-03-29 13:08:33 -07:00
Noah Limpert
1e07460d0e access of 4KiB spaced mem locations, aim to fill + evict a line of all 4 ways 2023-03-29 13:07:34 -07:00
David Harris
d059da6eca Turned on FS bit in fpu.S coverage test 2023-03-29 06:10:05 -07:00
Diego Herrera Vicioso
36d7ddf501 Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs. 2023-03-28 22:48:17 -07:00
David Harris
3dc1c6673d Started adding fpu fctrl tests 2023-03-28 21:13:25 -07:00
David Harris
2e5c50e24a Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
e8904411ce Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
David Harris
4594dffc7f Set PMP to allow all user/supervisor accesses in WALLY-init-lib 2023-03-28 06:46:11 -07:00
David Harris
2e238c15aa CSRS privileged coverage test 2023-03-28 04:37:56 -07:00
Jacob Pease
2d0199a354 Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore 2023-03-24 17:01:27 -05:00
Kip Macsai-Goren
106ed02a7e Revert "added premilinary boundary ccrossing cases" 
This reverts commit 7870148814.
 2023-03-24 11:27:41 -07:00
Kip Macsai-Goren
758da62a9f ported fixes to 32 bit tests 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
ff59fefcc9 replaced inerrupt tests with allowed versions 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
6f15ae1225 Added cause_s_soft_from_m_interrupt 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
7870148814 added premilinary boundary ccrossing cases 2023-03-24 11:22:39 -07:00
David Harris
f1e87c5e69 Start of EBU coverage tests 2023-03-24 08:12:02 -07:00
David Harris
b674ebf7f4 100% IEU coverage 2023-03-23 17:25:27 -07:00
David Harris
4e1bf6fbe0 Improved IEU and bitmanip test coverage 2023-03-23 14:24:41 -07:00
David Harris
121d1cea62 Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
David Harris
f4b252522e Coverage improvements 2023-03-23 09:06:05 -07:00
David Harris
ba4e0d2721 Merged bit manip 2023-03-23 06:55:29 -07:00
David Harris
610b50a693 Added new tests from class 2023-03-23 06:38:00 -07:00
Kip Macsai-Goren
c870b16c03 Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-22 14:11:58 -07:00
kipmacsaigoren
72028ab754 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 13:25:06 -07:00
Kip Macsai-Goren
44b5e234bd Removed unused ISA string from spike YAML 2023-03-22 13:23:52 -07:00
David Harris
3b3aa942c7 Added coverage tests to regression coverage 2023-03-22 13:00:10 -07:00
David Harris
31021265b8 Makefile improvements 2023-03-22 11:17:17 -07:00
Kevin Kim
1eb96e2221 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 10:33:15 -07:00
David Harris
4a1592ccf8 Building infrastructure for coverage directed tests 2023-03-22 04:37:13 -07:00
Kevin Kim
3f46dff23e Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
David Harris
18cc620e7f Added badinstr test file 2023-03-21 06:57:03 -07:00
kipmacsaigoren
2337e2ae16 Merge branch 'openhwgroup:main' into bit-manip 2023-03-07 21:29:03 -08:00
Kip Macsai-Goren
db6caedfec added in the CSR name for stimecmp(h) 2023-03-04 15:53:03 -08:00
Kip Macsai-Goren
ab6b953a4b removed changes to counteren from stimecmp tests 2023-03-04 15:46:57 -08:00
Kip Macsai-Goren
ac5c53a870 Added correct causing and handling of S time interrupts to test suite. 2023-03-04 15:04:17 -08:00
Jacob Pease
a7b547008a Commented out some fat filesystem error checks. 2023-02-28 12:18:13 -06:00
Jacob Pease
b7571a349d Preliminary work on new bootloader using new SD peripheral. 
Rewrote copyflash to take advantage of the new peripheral. The new
peripheral has the neat ability to use CMD18 in the SD card
specification, allowing us to load multiple blocks in succession,
ending the chain of CMD18 commands with a CMD17.
 2023-02-25 16:32:20 -06:00
Kip Macsai-Goren
ba3bfdf68b Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
0339dc5e78 added extra commands to make dut run work with spike for bit manip tests 2023-02-21 15:26:47 -08:00
Kip Macsai-Goren
d668c563f4 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
David Harris
99a1683f8e Debug test case updates 2023-02-21 09:33:36 -08:00
Kip Macsai-Goren
65a5b86dd8 Merge remote-tracking branch 'upstream/main' into main 2023-02-19 16:37:18 -08:00
David Harris
f0c0111ab0 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00
Kip Macsai-Goren
9c3aa55349 merge upstream synth changes 2023-02-18 14:35:19 -08:00
Kip Macsai-Goren
ea38e05773 fixed makefile for 32 bit arch tests, restored original make for all others 2023-02-17 09:57:56 -08:00
Kip Macsai-Goren
7344f3ef30 Modified arch64 tests to remove floating point and double tests from hanging make 2023-02-17 09:51:55 -08:00
Jacob Pease
45b264fa59 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
David Harris
2b80004db4 Debug test case update 2023-02-15 06:42:38 -08:00
Kevin Kim
4fed8d9196 added critical rsync command to python script and builds I-ext tests 
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
 2023-02-14 10:40:29 -08:00
Kevin Kim
5fed4c2c87 updated python script to generate bash file 2023-02-11 11:08:11 -08:00
Kevin Kim
7e4fc40dc7 changed python file to use WALLY env variable 2023-02-11 00:30:56 +00:00
Kip Macsai-Goren
76593cb282 Added necessary files to make bit make and run bit manipulation tests as part of regression 2023-02-10 10:35:19 -08:00
David Harris
9a6d7bb16d Added RVTEST_CASE to testgen header 2023-02-09 18:25:24 -08:00
David Harris
8fb513ad35 Moved test generators 2023-02-09 18:24:48 -08:00
David Harris
edbf962b5f Test gen header 2023-02-09 18:14:26 -08:00
David Harris
44fef2f2a1 debug simulating, produing discrepancy 2023-02-06 16:47:56 -08:00
David Harris
4c219de13d Fixed floating point crash in debug.S 2023-02-06 15:38:57 -08:00
David Harris
5256d3a625 More progress on debug.S, but it crashes in Spike 2023-02-04 09:59:22 -08:00
David Harris
43668a3fc5 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
2c69adc5f7 Started making debug testcase 2023-02-04 08:18:55 -08:00
David Harris
80f42a8638 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Jacob Pease
1952cfc9a4 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-30 14:55:22 -06:00
David Harris
4883351bd2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 18:18:53 -08:00
Kip Macsai-Goren
ee1bcf62ee Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. 2023-01-28 17:29:35 -08:00
Jacob Pease
973c932ae4 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-27 15:13:29 -06:00
Jacob Pease
264f0ba0da Removed IOBUF's from sdc_controller. 2023-01-27 14:35:34 -06:00
David Harris
d8f0e3dd70 Modified testgen to not produce reference outputs 2023-01-27 07:25:40 -08:00
David Harris
cea89f27cf Removed unused WALLY test references 2023-01-27 07:25:04 -08:00
David Harris
2af94bf283 Removed unused reference files 2023-01-27 07:21:55 -08:00
David Harris
37ba3d0fcd Removed f tests from rv32e 2023-01-27 06:15:20 -08:00
David Harris
7fbbed7927 Update riscof makefile to use rv32gc config 2023-01-27 05:57:58 -08:00
David Harris
b81b5781e1 Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested 2023-01-27 05:56:49 -08:00
Jacob Pease
9b612fbf6c Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-23 12:41:02 -06:00
David Harris
7d8a0d9615 Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases 2023-01-23 05:00:11 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Jacob Pease
b618518907 Fixed typos. Apparently `defube causes a weird vivado error. 2023-01-13 16:59:18 -06:00
Jacob Pease
fa087aeb30 Initial commit for the boot process. 2023-01-10 11:19:28 -06:00
Ross Thompson
97feea2f48 Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
a35fb3addd core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Kip Macsai-Goren
964084f0b3 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
a37bde7452 updated trap handler alignemnts to 64 bytes in priv tests 2022-12-22 14:23:04 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
David Harris
00ff823d84 Restored rv32d arch test after new push 2022-12-20 10:56:33 -08:00
Ross Thompson
c3b77926d5 I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
e8c1d14abb Have a basic cache test to fill all ways and sets. 2022-12-18 17:20:30 -06:00
Ross Thompson
7a352edf13 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
David Harris
643a2e7cf9 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
4c81b6fa5f added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
4ab99904a4 added all 32 bit tests to 64 bit periph tests except gpio 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
51e78d9e48 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
540d6c2f41 added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
fc05e27416 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Kip Macsai-Goren
9b1765ce92 added tests for invalid address being written to satp. Not passing regression 2022-11-27 13:22:35 -08:00
Kip Macsai-Goren
21e045eb7d added potential fix to overrun error and fifo interrupt error. test passes 2022-11-06 22:01:02 -08:00
Kip Macsai-Goren
90ef371abc fixed fifo timout handling. error now in data ready interrupt 2022-11-05 13:34:24 -07:00
Kip Macsai-Goren
c06da6e6fe fixed broken instructions so make works. 2022-11-03 23:06:20 +00:00
Ross Thompson
f1eb20ef4d Updated to put dtb into the rodata segment for our linker script. 2022-11-03 17:48:20 -05:00
Ross Thompson
1d7002e5c5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-03 17:36:04 -05:00
Ross Thompson
ccce0df535 Potentially a valid zero stage boot loader based on cva6. 2022-11-03 17:35:57 -05:00
Ross Thompson
103514a8e0 More outline for uart timeout interrupt. 2022-10-28 13:53:56 -05:00
Ross Thompson
21eca47d2e Untested change to uart test for outline of how to handle rx fifo timeout. 2022-10-28 13:31:16 -05:00
Kip Macsai-Goren
6e45698b86 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00
Ross Thompson
a59df0c77d Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Kip Macsai-Goren
c18c181fc0 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
e603973dff added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
9821a50eaa added mstatus uxl, sxl bit tests (not tested in regression yet) 2022-09-18 00:11:29 +00:00
Kip Macsai-Goren
0cc7f5719c ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
Kip Macsai-Goren
c5cbe43732 Fixed typos in existing endianness test 2022-09-18 00:09:52 +00:00
Kip Macsai-Goren
e6987524ab added full coverage of subword loads and stores to endianness test 2022-09-17 23:14:38 +00:00
Kip Macsai-Goren
cc7d1c8ef9 Created initial endianness tests 2022-09-16 01:06:26 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
4fb467ee8a Debugging plic-s test 2022-08-03 13:21:09 +00:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
cab0349701 Started plic-s tests 2022-08-03 03:48:08 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
429bdae1c4 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
b08c87cb47 Finished UART test 2022-07-27 04:06:59 +00:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
slmnemo
7348af7fd5 Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
a9d5805990 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-26 09:15:20 -07:00
slmnemo
5218865a7f Committing changes made to UART test 2022-07-26 09:14:40 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
c6a58eb5b6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
416f5edfe0 More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
7f7b3359b0 Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
d0aaae26fe fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Daniel Torres
4da96c5791 fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
141f2a40e4 UART updates and PMA fix 2022-07-22 14:49:03 -07:00
slmnemo
9cca567136 Added test comments to reference output 2022-07-22 12:35:59 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
d38369e8bf Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
8dcb794bbb added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
635a02cf6a made makefile more specific, just incase future additions 2022-07-21 12:50:02 -07:00
Daniel Torres
a8faddf81f removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00