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1833 Commits

Author SHA1 Message Date
cturek
04ac350a29 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
3a07d56d33 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
1b0f878c16 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
db5f3c15a4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
a86c9de36b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-02 04:28:50 -08:00
David Harris
6079a01bc8 update test list 2022-12-02 04:28:47 -08:00
Ross Thompson
602d191580 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 22:36:07 -06:00
David Harris
7c3e8553d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 16:27:36 -08:00
David Harris
0d23ab3ec1 reorder tests 2022-12-01 16:27:33 -08:00
Ross Thompson
3442b04f9e Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
David Harris
3a8602523e FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
e403800ce8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 11:47:54 -06:00
Ross Thompson
5025664cb0 Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
David Harris
28996d0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 08:15:51 -08:00
David Harris
1bd639be6d code cleanup 2022-12-01 08:15:48 -08:00
Ross Thompson
e6bd86f4fa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 17:19:04 -06:00
David Harris
4ddc8fd603 signal sufixes in integer division 2022-11-30 15:15:37 -08:00
Ross Thompson
fa22484cfe Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
Ross Thompson
2f582cd91f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00
Ross Thompson
a6355b1dcb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
0aa7ce0b24 Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
cedb234013 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
cturek
10c2d45888 div tests in sim-wally 2022-11-30 02:32:04 +00:00
Ross Thompson
453ea36512 Optimization of cacheway. 2022-11-29 18:30:47 -06:00
Ross Thompson
fbf543bf57 Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault. 2022-11-29 17:19:31 -06:00
Ross Thompson
0277227323 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 14:57:38 -06:00
Ross Thompson
b5718c9baa Fixed a bug with the replacement policy. It was updating the wrong set on load hits. 2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. 2022-11-29 14:09:48 -06:00
Kip Macsai-Goren
c7c578c104 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 10:43:44 -08:00
Kip Macsai-Goren
44ea8d8b22 added failing satp invalid tests to regression 2022-11-29 10:43:38 -08:00
Ross Thompson
78acd40424 Renamed signals in the cache. 2022-11-29 10:52:40 -06:00
Ross Thompson
6dd5668d21 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-22 18:07:32 -06:00
cturek
bdb9e24a66 Almost done with Int division 2022-11-22 22:22:59 +00:00
cturek
78c2ce5649 Updated testbench/wave for fdivsqrt new start signals 2022-11-22 22:22:26 +00:00
Ross Thompson
279f5bc615 Cleanup cacheLRU. 2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632 File name change for cachereplacement policy to cacheLRU 2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf Signal name changes for LRU. 2022-11-20 22:31:36 -06:00
Ross Thompson
00218d559f Missing a file. Last commit will fail. 2022-11-17 17:45:41 -06:00
Ross Thompson
0106777f02 Finally have the correct replacement policy implementation. 2022-11-17 17:36:37 -06:00
Ross Thompson
faa13a96e0 I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps. 2022-11-16 15:38:37 -06:00
Ross Thompson
22ad49eef2 Progress on the cache replacement policy implementation. 2022-11-16 15:35:34 -06:00
Ross Thompson
0796cd92fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-16 12:42:29 -06:00
Ross Thompson
42111db671 Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr. 2022-11-16 12:36:58 -06:00
David Harris
59335ac70f comment cleanup 2022-11-16 10:23:20 -08:00
David Harris
be9c618c94 Renamed DivBusy to FDivBusyE in FPU 2022-11-16 10:13:27 -08:00
David Harris
128cc86254 Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
Ross Thompson
1f21a2bab1 Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out. 2022-11-16 11:15:34 -06:00
cturek
ffd03e9548 Attempt to fix FPGA synth errors 2022-11-15 20:34:28 +00:00
cturek
98b66aab9f Fixed lint errors in postprocessing 2022-11-15 20:31:23 +00:00
Ross Thompson
3df51716b1 Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state. 2022-11-14 16:02:20 -06:00
Ross Thompson
b53f8eceef Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
284b97aff6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 13:48:56 -06:00
David Harris
6372139af4 Removed comment about nonexistent possible bug 2022-11-14 09:56:33 -08:00
David Harris
06dbed92c8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 09:52:24 -08:00
David Harris
f9202187ba Removed comment about nonexistent possible bug 2022-11-14 09:52:21 -08:00
Ross Thompson
13e6f7d80b Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18 Updated wave file. 2022-11-13 21:34:45 -06:00
cturek
abaa33b92a Added majority of combinational logic 2022-11-14 00:06:38 +00:00
cturek
6740d77b63 Added Quotient/Remainder calcs to normal termination 2022-11-13 23:44:34 +00:00
cturek
12e3646153 Added flops for n and m, added B=0 signal 2022-11-13 23:02:43 +00:00
cturek
f10700e666 Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
Ross Thompson
9d7ba19fe1 Changed IMWriteDataM to IHWriteDataM. 2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
hazard was not a straight forward merge.  I changed the way the LSU and IFU generate IFUStallF and LSUStallM.  They need to be suppressed by TrapM now.
 2022-11-13 12:25:22 -06:00
David Harris
84c4558641 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-13 04:23:26 -08:00
David Harris
879e62912b HPTW cleanup 2022-11-13 04:23:23 -08:00
David Harris
2ebdfa3f68 Comments about division hazards 2022-11-13 04:17:37 -08:00
Ross Thompson
54544ae251 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
cturek
4a8661649c Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
Ross Thompson
c028306ba3 Fixed name change in hptw. 2022-11-10 16:13:31 -06:00
Ross Thompson
d912981ec9 Wavefile update. 2022-11-10 15:48:06 -06:00
Ross Thompson
40367eaf45 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-10 15:46:25 -06:00
Ross Thompson
8658a25218 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91 Renamed CACHE_EVICT to CACHE_WRITEBACK. 2022-11-09 17:43:06 -06:00
cturek
9d30a832c3 Reoredered tests for arch32m 2022-11-09 18:42:00 +00:00
cturek
b723e16893 Fixed asign and bsign 2022-11-09 18:41:26 +00:00
Ross Thompson
be8e0eee1b Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc Moved lsuvirtmem muxes into hptw 2022-11-07 11:13:34 -08:00
Ross Thompson
d4f4950d2c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-07 09:10:51 -06:00
cturek
d571b5f9a5 propagated otfc swap to Rad2 and 4 qslc 2022-11-06 23:32:38 +00:00
Ross Thompson
e7d24609cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-06 17:22:25 -06:00
cturek
54f09f3616 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
c3e635c788 Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv 2022-11-06 22:40:21 +00:00
cturek
a49ea2a16d Added n and rightshiftx 2022-11-06 22:31:48 +00:00
cturek
350d4d254f p calculation 2022-11-06 22:24:21 +00:00
cturek
83051a5351 Changed lzc names, started int/fp size merge in preproc 2022-11-06 22:21:35 +00:00
cturek
2cbe2fd70b Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
cturek
6bc4c1318e Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
David Harris
53a88fec8f Reorder embench tests to prevent crash 2022-11-04 15:21:51 -07:00
David Harris
60cfa0d69c HPTW cleanup 2022-11-04 15:21:09 -07:00
Ross Thompson
44ee31a7f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-04 13:30:08 -05:00
cturek
06a9305766 renamed remOp to RemOp 2022-11-03 22:37:25 +00:00
cturek
e37f564e84 Added rem/div operation to postprocessor 2022-11-02 17:49:40 +00:00
Ross Thompson
44171c342d Reduced complexity of logic supressing cache operations. 2022-11-01 15:23:24 -05:00
cturek
e8d7607e87 Added buffered signals for int/fp 2022-10-28 21:47:24 +00:00
cturek
9f41e57f03 Config Cleanup 2022-10-27 22:38:56 +00:00
Ross Thompson
dc3a9f2342 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-26 14:48:50 -05:00
Ross Thompson
403434580d Fixed the uart transmit fifo overrun bug. 2022-10-26 14:48:09 -05:00
cturek
7301fc7f18 small signal cleanup 2022-10-26 18:42:49 +00:00
cturek
6caf7bb7e2 abs for int inputs 2022-10-26 16:18:05 +00:00
cturek
ec4646b412 Added signed division to fdivsqrt 2022-10-26 16:13:41 +00:00
cturek
71d16eacef unbroke DIVb 2022-10-26 16:11:51 +00:00
cturek
1febdb75b7 Config cleanup 2022-10-25 21:04:09 +00:00
Jacob Pease
160ca366c8 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
cturek
ff7d6b2932 Started Integer Preprocessing 2022-10-25 17:48:43 +00:00
Ross Thompson
9ba487c323 Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
7244ca1e7b Bit width error. 2022-10-24 13:48:47 -05:00
Ross Thompson
51408c620e Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks. 2022-10-23 13:46:50 -05:00
Ross Thompson
775309165b Small cleanup of interlockfsm. 2022-10-22 16:29:51 -05:00
Ross Thompson
a59df0c77d Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Ross Thompson
6696624971 comment updates. 2022-10-22 16:28:44 -05:00
Ross Thompson
12c5525807 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-22 16:27:30 -05:00
Ross Thompson
4db912678d Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline. 2022-10-22 16:27:20 -05:00
Jacob Pease
b1170ec7a2 Extended rxfifotimeout count to actually be 4 characters long. 2022-10-20 17:35:49 -05:00
Ross Thompson
2c5847b01f Moving interlockfsm changes to a temporary branch. 
reduced complexity of cache mux controls.
 2022-10-19 15:08:23 -05:00
Ross Thompson
9cadd4c6ec Broken don't use this state. 2022-10-19 14:31:22 -05:00
Ross Thompson
c6a9b17918 Noted possible bug with endianness during hptw. 
Minor complexity reduction in interlockfsm.  I think there is a lot of room to simplify.
 2022-10-19 12:20:19 -05:00
Ross Thompson
a53ca5c99f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-19 10:42:31 -05:00
Ross Thompson
d6f907f444 Sort of solved the bit width warning for dtim, irom ranges. 2022-10-19 10:42:19 -05:00
Ross Thompson
d4c5440f25 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-18 15:06:09 -05:00
Ross Thompson
92accfb1a6 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
47608df73e Possible fix for interrupt during a floating point divide. 2022-10-18 15:04:21 -05:00
Ross Thompson
65c2fe294a Merged cacheable with seluncachedadr. 2022-10-17 13:29:21 -05:00
David Harris
aa5fe52407 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-14 17:33:36 -07:00
David Harris
51b702fa17 Removed unused FPU waves 2022-10-14 17:33:32 -07:00
amaiuolo
56455bb9ad Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-10-13 22:36:57 +00:00
amaiuolo
1ae48e0edc added amaiuolo@hmc.edu 2022-10-13 22:36:52 +00:00
Ross Thompson
22603464ae Fixed uncached read bug introduced by yesterday's changes. 2022-10-13 11:11:36 -05:00
Ross Thompson
a4390dd07f Fixed LSU to correctly handle the difference between LLEN and AHBW. 2022-10-12 12:06:15 -05:00
Ross Thompson
b79872180b Actually fixed the bus width issue coming out of the cache. 
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
 2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
1dd9cb6697 quick fix to endianness wapping 64 bit reads in 32 bit confgs 2022-10-11 23:08:02 +00:00
Ross Thompson
7ddcf38fa9 Modified LSU to support DTIM without CSRs. 2022-10-11 14:05:20 -05:00
Ross Thompson
77de96905a Fixed first problem with the rv64i IROM. 2022-10-11 11:35:40 -05:00
Ross Thompson
dfd07a57fd Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. 
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
 2022-10-11 10:47:13 -05:00
David Harris
cc9a2fc62d Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU 2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2 Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width 2022-10-10 09:10:55 -07:00
David Harris
fde4832642 Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing 2022-10-10 07:12:37 -07:00
Ross Thompson
4bf5245f75 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-09 16:46:51 -05:00
Ross Thompson
9d23b0e6d6 Reorganized the configs. 2022-10-09 16:46:48 -05:00
David Harris
04dc0ac02c New fdivsqrtqsel4cmp module based on comparators rather than table lookup 2022-10-09 04:47:44 -07:00
David Harris
4f312ea2e7 Moved shift into divsqrt stage and cleaned up comments 2022-10-09 04:45:45 -07:00
David Harris
2aa43848f5 fdivsqrt code cleanup 2022-10-09 03:37:27 -07:00
Ross Thompson
6ff4abd4f7 Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS. 2022-10-05 15:46:53 -05:00
Ross Thompson
28584e4cca Fixed wally32e. 2022-10-05 15:37:01 -05:00
Ross Thompson
52a1d3dafe Name clarifications. 2022-10-05 15:36:56 -05:00
Ross Thompson
aa09b1ef16 Fixed bug with combined dtim+bus. 2022-10-05 15:16:01 -05:00
Ross Thompson
98521d073f Possibly have working dtim + bus config. 2022-10-05 15:08:20 -05:00
Ross Thompson
b01ee070bd Updated wavefile. 2022-10-05 14:55:40 -05:00
Ross Thompson
bf6f0e7219 Fixed bug in EBU. 2022-10-05 14:51:12 -05:00
Ross Thompson
cabcb5e89e Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. 
Don't use this commit as the rv32i tests are not passing.
 2022-10-05 14:51:02 -05:00
Ross Thompson
5e09d1cca7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-05 14:03:44 -05:00
David Harris
29033dc334 Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests. 2022-10-05 11:46:52 -07:00
Ross Thompson
ea70e1c598 Optimized the ebu's beat counting. 2022-10-05 10:58:23 -05:00
Ross Thompson
294645a49f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-04 17:38:49 -05:00
Ross Thompson
494f8b94f4 Reordered the eviction and fetch in cache so it follows a more logical order. 2022-10-04 17:36:07 -05:00
Ross Thompson
18e739befc Modified cache lru to not have the delayed write. 2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
c18c181fc0 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
3f6d05f7a2 addded renamed file 2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
9a0b98037b Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546 Renamed endianswap to match module name 2022-10-04 17:33:49 +00:00
Ross Thompson
0ed0c18aa1 Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered. 2022-10-02 16:21:21 -05:00
Ross Thompson
d08c29e3c5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-01 15:01:22 -05:00
Ross Thompson
41ab4850e1 Disable IFU bus access on TrapM. 2022-10-01 14:54:16 -05:00
Ross Thompson
e27fcb1577 Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage. 2022-09-29 18:37:34 -05:00
David Harris
657f16dfd1 Adding start signals for integer divider to fdivsqrt 2022-09-29 16:30:25 -07:00
Ross Thompson
2c0132aa9c Renamed signals in EBU. 2022-09-29 18:29:38 -05:00
cturek
e8a869e0e7 Added integer inputs and flags to divsqrt 2022-09-29 23:08:27 +00:00
Ross Thompson
58d597b614 Simplification to EBU. 2022-09-29 18:06:34 -05:00
Ross Thompson
d81af3bca8 Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore. 2022-09-29 11:54:03 -05:00
Ross Thompson
32449dfe97 Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
Ross Thompson
4db017dac3 Possible fix for ifu/lsu arbiration issue. 2022-09-27 17:24:35 -05:00
Ross Thompson
4062fe56c0 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e Found a hidden bug in the cache to bus fsm interlock. 2022-09-26 17:41:30 -05:00
Ross Thompson
996c4ca8f2 renamed ahbmulticontroller to ebu. 2022-09-26 14:37:18 -05:00
Ross Thompson
8ed173a5f5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-26 12:49:16 -05:00
Ross Thompson
0fcc314d06 Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00
David Harris
713df785d1 changed always_ff to always in sram1p1rw to fix testbench complaint 2022-09-25 19:56:40 -07:00
Ross Thompson
38edbde966 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
2eaf3af6c7 Removed the write first sram model. 2022-09-22 16:12:08 -05:00
Ross Thompson
cec50ce208 The valid and dirty bits match the SRAM implementation now. 2022-09-22 16:09:09 -05:00
Ross Thompson
b48d6b5e1f Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
89e6ddfa4e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 18:24:06 -05:00
Ross Thompson
99e01dd31f Cleaned up the IFU and LSU around dtim and irom address calculation. 2022-09-21 18:23:56 -05:00
David Harris
d6297a2f2e For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc 2022-09-21 13:30:35 -07:00
David Harris
e49e99548a Fixed testbench-fp to support all again 2022-09-21 13:19:48 -07:00
David Harris
46680b80a7 Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
Ross Thompson
f57b0b9950 Updated IROMAdr logic. 2022-09-21 12:42:43 -05:00
Ross Thompson
0add170b44 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:36:52 -05:00
Ross Thompson
3fb0a13fe2 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
David Harris
030fb79a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 10:35:11 -07:00
David Harris
cb4c3ff1ce Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest 2022-09-21 10:35:08 -07:00
Ross Thompson
66c45949b5 Renamed brom1p1r to rom1p1r. 
removed used file bram2p1r1w.sv.
 2022-09-21 12:31:20 -05:00
Ross Thompson
832658838d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:20:12 -05:00
Ross Thompson
ac864a6ca3 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
c0884ecc63 Modified sram1p1rw to support 3 different implementation styles. 
SRAM, Read first, and Write first.
 2022-09-21 11:26:00 -05:00
David Harris
129b9343fe commented SpecialCase 2022-09-21 05:02:08 -07:00
David Harris
5e1932c649 Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc 2022-09-21 04:55:43 -07:00
David Harris
f7d272c315 Gated sticky bit in fdiv with SpecialCase 2022-09-20 20:05:00 -07:00
David Harris
1cbdd20778 Restored radix 2 to pass regression 2022-09-20 19:30:16 -07:00
David Harris
3b98881c4e renamed u to udigit to avoid conflict with U 2022-09-20 19:29:23 -07:00
cturek
6e300a667e Fixed R4 Sqrt overshifting 2022-09-21 00:05:36 +00:00
cturek
c3c764f0ba Fixed fgen4 2022-09-20 20:00:01 +00:00
Ross Thompson
980b35d585 Merge branch 'tempMain' into main 2022-09-20 13:57:38 -05:00
Ross Thompson
1658edd21e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 11:56:53 -05:00
Ross Thompson
426ec6222b Added chip enables to sram. 2022-09-20 10:49:14 -05:00
David Harris
11fb39b373 Define LOGNORMSHIFTSZ 2022-09-20 08:31:57 -07:00
Ross Thompson
822d989383 Added comment. 2022-09-20 09:49:53 -05:00
Ross Thompson
4c3c517322 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 09:47:16 -05:00
David Harris
00c15ec472 renamed q to u for unified digit selection 2022-09-20 04:35:14 -07:00
David Harris
d01588d693 Removed D2 and D2b from radix2 stage 2022-09-20 04:20:38 -07:00
David Harris
2ea7df1b6d Simplified UM initialization 2022-09-20 04:18:12 -07:00
David Harris
0d5e80a4f0 fdivsqrtfgen4 comments 2022-09-20 04:13:21 -07:00
David Harris
653c458241 Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
David Harris
0ec1886b89 Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
David Harris
a05b6486b1 Simplified fdivsqrtpostproc QmM logic 2022-09-20 03:30:18 -07:00
David Harris
87cde2c427 make QmM size b+1 indpenedent of radix 2022-09-20 03:25:09 -07:00
David Harris
e455f41b97 clean up divshiftcalc 2022-09-20 03:19:50 -07:00
David Harris
211705eca2 clean up divshiftcalc 2022-09-20 03:17:29 -07:00
David Harris
d3b2a192eb clean up divshiftcalc 2022-09-20 03:13:11 -07:00
David Harris
f5083803c2 clean up divshiftcalc 2022-09-20 03:08:25 -07:00
David Harris
2faa0d14be Cleaning up divshiftcalc LOGNORMSHIFTSZ 2022-09-20 02:35:01 -07:00
Jacob Pease
1e7bbe1a87 Fixed rxfifotimeout restarting for every new character, even when already high. 2022-09-19 18:00:30 -05:00
cturek
019a6eb9f5 Radix 4 sqrt passing first two tests 2022-09-19 21:26:32 +00:00
Ross Thompson
bcca9a62c5 Fixed up IFU ahb interface names and widths. 2022-09-19 10:54:22 -05:00
David Harris
8e90862dad Removed EarlyTermShift from fdiv 2022-09-19 08:44:23 -07:00
David Harris
73ceb4590c Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
David Harris
3cf6becaf4 fdivsqrtiter simplification 2022-09-19 01:08:01 -07:00
David Harris
e840edc4e6 Reduced number of cycles needed for division 2022-09-19 01:02:04 -07:00
David Harris
d6f1453275 Cleaned up otfc4 2022-09-19 00:58:20 -07:00
David Harris
309995a6e9 OTFC simplification 2022-09-19 00:51:56 -07:00
David Harris
59b6346a28 Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
David Harris
e764d4322c fdiv cleanup 2022-09-19 00:32:34 -07:00
David Harris
cf0c20d489 Division working again for radix 2 with unified OTFC 2022-09-19 00:30:30 -07:00
David Harris
b636072914 Unified on-the-fly conversion working for radix 2; broke radix-4 division 2022-09-19 00:04:00 -07:00
David Harris
4dbe1035cb Added 2 bits to C to initialize properly 2022-09-18 22:44:22 -07:00
David Harris
f202eb0f6f Added 2 bits to C to initialize properly 2022-09-18 22:42:35 -07:00
David Harris
cff3c2535d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-18 21:27:36 -07:00
David Harris
498c053aab FP testbench 2022-09-18 21:27:21 -07:00
David Harris
f38bb5b32e Divide testfloat starts with half-precision tests 2022-09-18 06:46:47 -07:00
Ross Thompson
57c366c1b2 Removed NonIROM and NonDTIM select signals from IFU and LSU. 2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f Found the ahb burst bug. 
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests.  It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads.  The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads.  In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
 2022-09-17 20:30:01 -05:00
David Harris
b74a68ff0f Reduced number of cycles required for lower-precision sqrt 2022-09-17 09:55:34 -07:00
David Harris
ac78823f6c Starting to adust number of cycles for division/sqrt 2022-09-17 05:58:59 -07:00
cturek
79addec27a Fixed j1 to align with new C reg 2022-09-16 02:15:48 +00:00
Kip Macsai-Goren
cc7d1c8ef9 Created initial endianness tests 2022-09-16 01:06:26 +00:00
David Harris
8f2b3b2387 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-15 12:49:21 -07:00
David Harris
94dca9194e renamed endianswap 2022-09-15 12:49:18 -07:00
Ross Thompson
38e114a6c0 Fixed subword read to work with bigendian. 2022-09-15 14:08:04 -05:00
David Harris
29d9ded25c FDIVSQRT cleanup 2022-09-15 09:10:57 -07:00
Ross Thompson
cea012a640 renamed multimanager to multicontroller. 2022-09-14 14:03:37 -05:00
Ross Thompson
bf6468a24c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 13:59:22 -05:00
cturek
da67e02392 Added shift for radix 4 sqrt 2022-09-14 17:34:24 +00:00
cturek
47d02db2eb Moved X-1 to preproc 2022-09-14 17:26:56 +00:00
cturek
fe77b5e37b Delete srt 2022-09-14 17:02:42 +00:00
cturek
4f3baea0fc removed unnecessary XZero from wsmux 2022-09-14 16:59:52 +00:00
David Harris
14bbd07e63 ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 09:42:17 -07:00
Ross Thompson
2c86badeb2 pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
Ross Thompson
c7d3580637 Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
David Harris
1495305045 Removed unused signals 2022-09-12 11:35:35 -07:00
David Harris
7197a6de44 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 16:05:58 -07:00
David Harris
7639c05e51 Moved C to shift before rather than after using in an iteration 2022-09-08 16:05:53 -07:00
David Harris
7ba9b0b349 divsqrt comment cleanup 2022-09-08 15:40:42 -07:00
Ross Thompson
c4a7d3c147 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 17:15:46 -05:00
David Harris
5ea82cff33 CSA-based completion detection 2022-09-08 14:58:08 -07:00
Ross Thompson
7f1ae039b0 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
0904951a8c Oups the ahbinterface.sv was accidentally named abhinterface.sv. 2022-09-08 13:21:37 -05:00
Ross Thompson
6e8d97e921 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 16:36:51 -05:00
Ross Thompson
f4e3036593 Oups fixed order of ending swap with mux between cache and fetch buffer. 2022-09-07 16:29:47 -05:00
David Harris
2d5e7827df Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
David Harris
c730ddf74a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 11:11:39 -07:00
David Harris
7a29f9c95b Running 16-bit square root cases first in testfloat 2022-09-07 11:11:35 -07:00
Ross Thompson
0615798467 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 12:26:50 -05:00
David Harris
ce6e153b15 Run 16-bit fsqrt tests first 2022-09-07 10:26:09 -07:00
Ross Thompson
83306ec238 Named change for ahb tests to be less annoying. 2022-09-07 12:24:41 -05:00
David Harris
838d98cf4b Preprocessing cleanup 2022-09-07 10:21:27 -07:00
Ross Thompson
3571fb18c2 Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
David Harris
dff9416a33 Added rv32i config for regression of wally32periph 2022-09-07 09:37:59 -07:00
Ross Thompson
5a0cda9860 Merge branch 'multimanager' into main 2022-09-07 10:54:27 -05:00
David Harris
c8e0ea067e Continued simplifying fdivsqrt postprocessing 2022-09-07 07:02:22 -07:00
David Harris
b0ff3a0952 Continued simplifying fdivsqrt postprocessing 2022-09-07 07:00:13 -07:00
David Harris
9e7926e8d7 Moving postprocessing into postproc block 2022-09-07 06:42:37 -07:00
David Harris
c39e71f168 fdivsqrtfsm cleanup 2022-09-07 06:32:07 -07:00
David Harris
027b303b20 fdivsqrtfsm cleanup 2022-09-07 06:27:01 -07:00
David Harris
19e449b83d Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00
Ross Thompson
7ad7cea25b James found a bug in synchronizer. Was not actually back to back flip flops. 2022-09-06 15:06:54 -05:00
Ross Thompson
bc15f6c5e4 Added logic to make burst optional. 2022-09-06 09:21:21 -05:00
Ross Thompson
68a200d728 Added generate around the longer latency version of the ram_ahb.sv 2022-09-06 09:21:03 -05:00
Ross Thompson
20643ffc4a Names changes. 2022-09-05 20:49:35 -05:00
Ross Thompson
2554f96662 Cleaned up hacks to ram. 2022-09-04 14:52:40 -05:00
Ross Thompson
c87268baf1 Modified ram_ahb to work with different latencies. 2022-09-04 14:46:15 -05:00
Ross Thompson
f9daa7f6b9 Progress towards fixing the select HREADY muxing in uncore. 2022-09-04 13:07:49 -05:00
Ross Thompson
221367efb9 Disabled AHB burst mode, which discovered a bug. 
Multimanger bug in how back to back requests were arbitrated.
 2022-09-03 22:31:41 -05:00
cturek
254bb8e0a0 Old changes to old files 2022-09-03 22:09:55 +00:00
Ross Thompson
d601fdf186 Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle. 2022-09-02 19:58:41 -05:00
Ross Thompson
00cffb0aa5 Renamed state in buscachefsm to match AHB phases. 2022-09-02 17:17:40 -05:00
Ross Thompson
6f2acf678c Renamed states in busfsm to match AHB phases and book names. 2022-09-02 17:12:36 -05:00
Ross Thompson
6f366c643d Possible fix for AHB trailing ~HREADY bug. 2022-09-02 16:58:35 -05:00
Ross Thompson
3361a06c62 Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 16:31:07 -05:00
Ross Thompson
5d2b299182 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00