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Reduced number of cycles needed for division

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This commit is contained in:
David Harris 2022-09-19 01:02:04 -07:00
parent d6f1453275
commit e840edc4e6
1 changed files with 1 additions and 2 deletions
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pipelined/src/fpu/fdivsqrtfsm.sv
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@ -95,8 +95,7 @@ module fdivsqrtfsm(
always_comb begin
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
if (SqrtE) cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); // ceiling(fbits / r*k)
else cycles = `FPDUR; // *** line above should work once otfc is used to put results in upper bits
cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
end
/* verilator lint_on WIDTH */