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https://github.com/openhwgroup/cvw
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Changed lzc names, started int/fp size merge in preproc
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@ -127,7 +127,7 @@
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`define DURLEN ($clog2(`FPDUR+1))
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`define QLEN (`FPDUR*`LOGR*`DIVCOPIES)
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`define DIVb (`QLEN-1)
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`define DIVBLEN ($clog2(`DIVb))
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`define DIVBLEN ($clog2(`DIVb+1)-1)
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`define USE_SRAM 0
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@ -51,7 +51,7 @@ module fdivsqrtpreproc (
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logic [`NF-1:0] PreprocB, PreprocY;
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logic [`NF+1:0] SqrtX;
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logic [`DIVb+3:0] DivX;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [`DIVBLEN:0] L;
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logic [`NE+1:0] Qe;
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// Intdiv signals
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logic [`DIVb-1:0] ZeroBufX, ZeroBufY;
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@ -75,13 +75,13 @@ module fdivsqrtpreproc (
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assign ZeroBufX = MDUE ? {PosA, {`DIVb-`XLEN{1'b0}}} : {Xm, {`DIVb-`NF-1{1'b0}}};
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assign ZeroBufY = MDUE ? {PosB, {`DIVb-`XLEN{1'b0}}} : {Ym, {`DIVb-`NF-1{1'b0}}};
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lzc #(`NF+1) lzcX (Xm, XZeroCnt);
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lzc #(`NF+1) lzcY (Ym, YZeroCnt);
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lzc #(`DIVb) lzcX (ZeroBufX, L);
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lzc #(`DIVb) lzcY (ZeroBufY, m);
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assign PreprocX = Xm[`NF-1:0]<<XZeroCnt;
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assign PreprocY = Ym[`NF-1:0]<<YZeroCnt;
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assign PreprocX = Xm[`NF-1:0]<<L;
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assign PreprocY = Ym[`NF-1:0]<<m;
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// assign ZeroDiff = YZeroCnt - XZeroCnt;
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// assign ZeroDiff = m - L;
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// assign p = ZeroDiff[`DIVBLEN] ? '0 : ZeroDiff;
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// assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
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@ -91,7 +91,7 @@ module fdivsqrtpreproc (
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// assign IntBits = (`DIVBLEN)'(`RK) + p;
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// assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]};
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assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
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assign SqrtX = Xe[0]^L[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
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assign DivX = {3'b000, ~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
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// *** explain why X is shifted between radices (initial assignment of WS=RX)
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@ -110,17 +110,17 @@ module fdivsqrtpreproc (
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// r = 1 or 2
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// DIVRESLEN/(r*`DIVCOPIES)
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flopen #(`NE+2) expflop(clk, DivStartE, Qe, QeM);
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expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .XZeroCnt, .YZeroCnt, .Qe);
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expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m, .Qe);
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endmodule
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module expcalc(
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input logic [`FMTBITS-1:0] Fmt,
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input logic [`FMTBITS-1:0] Fmt,
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input logic [`NE-1:0] Xe, Ye,
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input logic Sqrt,
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input logic XZero,
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input logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt,
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output logic [`NE+1:0] Qe
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input logic Sqrt,
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input logic XZero,
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input logic [`DIVBLEN:0] L, m,
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output logic [`NE+1:0] Qe
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);
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logic [`NE-2:0] Bias;
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logic [`NE+1:0] SXExp;
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@ -151,10 +151,10 @@ module expcalc(
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2'h2: Bias = (`NE-1)'(`H_BIAS);
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endcase
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end
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assign SXExp = {2'b0, Xe} - {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, XZeroCnt} - (`NE+1)'(`BIAS);
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assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, L} - (`NE+2)'(`BIAS);
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assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
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// correct exponent for denormalized input's normalization shifts
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assign DExp = ({2'b0, Xe} - {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, XZeroCnt} - {2'b0, Ye} + {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, YZeroCnt} + {3'b0, Bias})&{`NE+2{~XZero}};
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assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, L} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
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assign Qe = Sqrt ? SExp : DExp;
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endmodule
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