Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Division working again for radix 2 with unified OTFC

Browse Source
This commit is contained in:
David Harris 2022-09-19 00:30:30 -07:00
parent b636072914
commit cf0c20d489
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/fpu/fdivsqrtiter.sv
View File

@ -104,7 +104,7 @@ module fdivsqrtiter(
logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper;
assign initCSqrt = 2'b11;
assign initCDiv2 = 2'b10;
assign initCDiv4 = 2'b00;
assign initCDiv4 = 2'b10; // *** not sure why this works; seems like it should be 00 for initializing to -4
assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2;
assign initC = {initCUpper, {`DIVb{1'b0}}};

3
pipelined/src/fpu/fdivsqrtstage4.sv
View File

@ -53,7 +53,6 @@ module fdivsqrtstage4 (
logic [`DIVb+3:0] AddIn;
logic [4:0] Smsbs;
logic CarryIn;
assign CNext = {2'b11, C[`DIVb+1:2]};
// Qmient Selection logic
@ -86,6 +85,8 @@ module fdivsqrtstage4 (
otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .S, .SM, .SNext, .SMNext);
assign qn = 0; // unused for radix 4
endmodule