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https://github.com/openhwgroup/cvw
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
832658838d
@ -102,7 +102,7 @@
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`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6))
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// division constants
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`define RADIX 32'h2
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`define RADIX 32'h4
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`define DIVCOPIES 32'h3
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`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3))
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// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
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@ -61,6 +61,7 @@ module fdivsqrt(
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logic [`DIVb+1:0] FirstC;
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logic Firstun;
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logic WZero;
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logic SpecialCaseM;
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fdivsqrtpreproc fdivsqrtpreproc(
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.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
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@ -69,11 +70,11 @@ module fdivsqrt(
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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.DivBusy, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
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.XNaNE, .YNaNE,
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.XInfE, .YInfE, .WZero);
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.XInfE, .YInfE, .WZero, .SpecialCaseM);
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fdivsqrtiter fdivsqrtiter(
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.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
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.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN,
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.DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
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.DivBusy);
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fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .QmM, .WZero, .DivSM);
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fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZero, .DivSM);
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endmodule
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@ -31,7 +31,7 @@
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`include "wally-config.vh"
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module fdivsqrtfgen4 (
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input logic [3:0] u,
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input logic [3:0] udigit,
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input logic [`DIVb+3:0] C, U, UM,
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output logic [`DIVb+3:0] F
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);
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@ -47,9 +47,9 @@ module fdivsqrtfgen4 (
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// Choose which adder input will be used
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always_comb
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if (u[3]) F = F2;
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else if (u[2]) F = F1;
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else if (U[1]) F = FN1;
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else if (u[0]) F = FN2;
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if (udigit[3]) F = F2;
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else if (udigit[2]) F = F1;
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else if (udigit[1]) F = FN1;
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else if (udigit[0]) F = FN2;
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else F = F0;
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endmodule
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@ -44,18 +44,20 @@ module fdivsqrtfsm(
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input logic StallM,
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input logic WZero,
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output logic DivDone,
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output logic DivBusy
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output logic DivBusy,
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output logic SpecialCaseM
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);
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typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
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statetype state;
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logic [`DURLEN-1:0] step;
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logic SpecialCase;
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logic [`DURLEN-1:0] cycles;
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logic SpecialCaseE;
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// terminate immediately on special cases
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assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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assign SpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
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// DIVN = `NF+3
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// NS = NF + 1
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@ -103,7 +105,7 @@ module fdivsqrtfsm(
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step <= cycles; // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1
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// $display("Setting Nf = %d fbits %d cycles = %d FmtE %d FPSIZES = %d Q_NF = %d num = %d denom = %d\n", Nf, fbits, cycles, FmtE, `FPSIZES, `Q_NF,
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// (fbits +(`LOGR*`DIVCOPIES)-1), (`LOGR*`DIVCOPIES));
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if (SpecialCase) state <= #1 DONE;
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if (SpecialCaseE) state <= #1 DONE;
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else state <= #1 BUSY;
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end else if (DivDone) begin
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if (StallM) state <= #1 DONE;
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@ -37,6 +37,7 @@ module fdivsqrtpostproc(
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input logic [`DIVb+1:0] FirstC,
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input logic Firstun,
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input logic SqrtM,
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input logic SpecialCaseM,
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output logic [`DIVb:0] QmM,
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output logic WZero,
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output logic DivSM
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@ -64,7 +65,7 @@ module fdivsqrtpostproc(
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end else begin
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assign WZero = weq0;
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end
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assign DivSM = ~WZero;
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assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
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// Determine if sticky bit is negative
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assign W = WC+WS;
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@ -61,6 +61,8 @@ module fdivsqrtpreproc (
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assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
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assign DivX = {3'b000, ~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
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// *** explain why X is shifted between radices
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if (`RADIX == 2) assign X = Sqrt ? {3'b111, SqrtX, {`DIVb-1-`NF{1'b0}}} : DivX;
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else assign X = Sqrt ? {2'b11, SqrtX, {`DIVb-1-`NF{1'b0}}, 1'b0} : DivX;
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assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
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@ -35,7 +35,7 @@ module fdivsqrtqsel4 (
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input logic [4:0] Smsbs,
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input logic [`DIVb+3:0] WS, WC,
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input logic Sqrt, j1,
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output logic [3:0] u
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output logic [3:0] udigit
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);
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logic [6:0] Wmsbs;
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logic [7:0] PreWmsbs;
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@ -107,6 +107,6 @@ module fdivsqrtqsel4 (
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else if (Smsbs == 5'b10000) A = 3'b111;
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else A = Smsbs[2:0];
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end else A = Dmsbs;
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assign u = USel4[{A,Wmsbs}];
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assign udigit = USel4[{A,Wmsbs}];
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endmodule
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@ -46,7 +46,7 @@ module fdivsqrtstage4 (
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/* verilator lint_on UNOPTFLAT */
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logic [`DIVb+3:0] Dsel;
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logic [3:0] u;
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logic [3:0] udigit;
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logic [`DIVb+3:0] F;
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logic [`DIVb+3:0] AddIn;
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logic [4:0] Smsbs;
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@ -61,11 +61,11 @@ module fdivsqrtstage4 (
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// 0010 = -1
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// 0001 = -2
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assign Smsbs = U[`DIVb:`DIVb-4];
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fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .u);
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fdivsqrtfgen4 fgen4(.u, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
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fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .udigit);
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fdivsqrtfgen4 fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
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always_comb
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case (u)
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case (udigit)
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4'b1000: Dsel = DBar2;
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4'b0100: Dsel = DBar;
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4'b0000: Dsel = '0;
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@ -77,10 +77,10 @@ module fdivsqrtstage4 (
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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assign AddIn = SqrtM ? F : Dsel;
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assign CarryIn = ~SqrtM & (u[3] | u[2]); // +1 for 2's complement of -D and -2D
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assign CarryIn = ~SqrtM & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D
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csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
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fdivsqrtuotfc4 fdivsqrtuotfc4(.u, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
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fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
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assign un = 0; // unused for radix 4
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endmodule
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@ -31,7 +31,7 @@
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`include "wally-config.vh"
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module fdivsqrtuotfc4(
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input logic [3:0] u,
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input logic [3:0] udigit,
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input logic Sqrt,
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input logic [`DIVb:0] U, UM,
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input logic [`DIVb:0] C,
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@ -47,19 +47,19 @@ module fdivsqrtuotfc4(
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assign K3 = (C & ~(C << 2)); // 3K
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always_comb begin
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if (u[3]) begin
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if (udigit[3]) begin
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UNext = U | K2;
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UMNext = U | K1;
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end else if (u[2]) begin
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end else if (udigit[2]) begin
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UNext = U | K1;
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UMNext = U;
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end else if (u[1]) begin
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end else if (udigit[1]) begin
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UNext = UM | K3;
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UMNext = UM | K2;
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end else if (u[0]) begin
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end else if (udigit[0]) begin
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UNext = UM | K2;
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UMNext = UM | K1;
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end else begin // digit = 0
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end else begin // udigit = 0
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UNext = U;
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UMNext = UM | K3;
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end
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@ -73,8 +73,10 @@ module divshiftcalc(
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assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0;
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assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift;
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// *** explain why radix 4 division needs a left shift by 1
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// *** can this shift be moved into the shiftcorrection logic?
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if (`RADIX == 4)
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assign DivShiftIn = {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}};
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assign DivShiftIn = Sqrt ? {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}} : {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}};
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else
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assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
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endmodule
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@ -128,10 +128,12 @@ module flags(
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// | | | | | and if the input isnt infinity or NaN
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// | | | | | |
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assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&G)))&(R|S|G))&~(InfIn|NaNIn|DivByZero|Invalid);
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//assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&G)))&(R|S|G))&~(InfIn|NaNIn|DivByZero|Invalid|XZero);
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// Set Inexact flag if the res is diffrent from what would be outputed given infinite precision
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// - Don't set the underflow flag if an underflowed res isn't outputed
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assign FpInexact = (S|G|Overflow|R)&~(InfIn|NaNIn|DivByZero|Invalid);
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//assign FpInexact = (S|G|Overflow|R)&~(InfIn|NaNIn|DivByZero|Invalid|XZero);
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// if the res is too small to be represented and not 0
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// | and if the res is not invalid (outside the integer bounds)
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