Moved fpu modules into subdirectories

2025-02-11 06:05:49 +00:00 · 2022-09-20 04:12:05 -07:00 · 2022-09-20 04:12:05 -07:00 · 653c458241
commit 653c458241
parent 0ec1886b89
31 changed files with 1 additions and 1 deletions
--- a/pipelined/regression/testfloat.do
+++ b/pipelined/regression/testfloat.do
@ -32,7 +32,7 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 # $num = the added words after the call
-vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
+vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 

 vsim -voptargs=+acc work.testbenchfp -G TEST=$2

--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
--- a/pipelined/src/fpu/fma/fma.sv
+++ b/pipelined/src/fpu/fma/fma.sv
--- a/pipelined/src/fpu/fma/fmaadd.sv
+++ b/pipelined/src/fpu/fma/fmaadd.sv
--- a/pipelined/src/fpu/fma/fmaalign.sv
+++ b/pipelined/src/fpu/fma/fmaalign.sv
--- a/pipelined/src/fpu/fma/fmaexpadd.sv
+++ b/pipelined/src/fpu/fma/fmaexpadd.sv
--- a/pipelined/src/fpu/fma/fmalza.sv
+++ b/pipelined/src/fpu/fma/fmalza.sv
--- a/pipelined/src/fpu/fma/fmamult.sv
+++ b/pipelined/src/fpu/fma/fmamult.sv
--- a/pipelined/src/fpu/fma/fmasign.sv
+++ b/pipelined/src/fpu/fma/fmasign.sv
--- a/pipelined/src/fpu/postproc/cvtshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv
--- a/pipelined/src/fpu/postproc/divshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
--- a/pipelined/src/fpu/postproc/fmashiftcalc.sv
+++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv
--- a/pipelined/src/fpu/postproc/negateintres.sv
+++ b/pipelined/src/fpu/postproc/negateintres.sv
--- a/pipelined/src/fpu/postproc/postprocess.sv
+++ b/pipelined/src/fpu/postproc/postprocess.sv
--- a/pipelined/src/fpu/postproc/resultsign.sv
+++ b/pipelined/src/fpu/postproc/resultsign.sv
--- a/pipelined/src/fpu/postproc/round.sv
+++ b/pipelined/src/fpu/postproc/round.sv
--- a/pipelined/src/fpu/postproc/roundsign.sv
+++ b/pipelined/src/fpu/postproc/roundsign.sv
--- a/pipelined/src/fpu/postproc/shiftcorrection.sv
+++ b/pipelined/src/fpu/postproc/shiftcorrection.sv
--- a/pipelined/src/fpu/postproc/specialcase.sv
+++ b/pipelined/src/fpu/postproc/specialcase.sv