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I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.

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This commit is contained in:
Ross Thompson 2022-11-16 15:38:37 -06:00
parent 22ad49eef2
commit faa13a96e0
2 changed files with 4 additions and 4 deletions
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6
pipelined/src/ifu/ifu.sv
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@ -221,7 +221,7 @@ module ifu (
cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
icache(.clk, .reset, .FlushStage(FlushW), .CPUBusy,
icache(.clk, .reset, .FlushStage(TrapM), .CPUBusy,
.FetchBuffer, .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheBusRW,
@ -238,7 +238,7 @@ module ifu (
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
.HRDATA,
.Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
.Flush(TrapM), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
@ -257,7 +257,7 @@ module ifu (
// assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM};
assign IFUHSIZE = 3'b010;
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushW), .HRESETn(~reset), .HREADY(IFUHREADY),
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY),
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));

2
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -246,7 +246,7 @@ module wallypipelinedcore (
lsu lsu(
.clk, .reset, .StallM, .FlushM, .StallW,
.FlushW,
.FlushW(TrapM),
// CPU interface
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
.AtomicM,