Ross Thompson b79872180b Actually fixed the bus width issue coming out of the cache. ... The root cause is the ahb bus width can be different from LLEN. If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well. Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.		2022-10-12 11:33:10 -05:00
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config	Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.	2022-10-11 10:47:13 -05:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.	2022-10-11 10:47:13 -05:00
src	Actually fixed the bus width issue coming out of the cache.	2022-10-12 11:33:10 -05:00
testbench	fixed endianness mstatush problem, passes make, not regression	2022-10-04 17:37:39 +00:00