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Fixed a bug with the replacement policy. It was updating the wrong set on load hits.

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This commit is contained in:
Ross Thompson 2022-11-29 14:51:09 -06:00
parent 96cc4c7ebe
commit b5718c9baa
3 changed files with 10 additions and 7 deletions
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5
pipelined/src/cache/cache.sv vendored
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@ -129,10 +129,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
CacheWays[NUMWAYS-1:0](.clk, .reset, .ce, .CAdr, .PAdr, .LineWriteData, .LineByteMask,
.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .VictimDirtyWay, .VictimTagWay, .FlushStage,
.Invalidate(InvalidateCache));
.InvalidateCache);
if(NUMWAYS > 1) begin:vict
cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
.clk, .reset, .ce, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid);
.clk, .reset, .ce, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage),
.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
end else assign VictimWay = 1'b1; // one hot.
assign CacheHit = | HitWay;
assign VictimDirty = | VictimDirtyWay;

8
pipelined/src/cache/cacheLRU.sv vendored
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@ -37,7 +37,8 @@ module cacheLRU
input logic [NUMWAYS-1:0] ValidWay,
output logic [NUMWAYS-1:0] VictimWay,
input logic [SETLEN-1:0] CAdr,
input logic LRUWriteEn, SetValid);
input logic [SETLEN-1:0] PAdr,
input logic LRUWriteEn, SetValid, InvalidateCache);
logic [NUMWAYS-2:0] LRUMemory [NUMLINES-1:0];
logic [NUMWAYS-2:0] CurrLRU;
@ -120,8 +121,9 @@ module cacheLRU
always_ff @(posedge clk) begin
if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
if(ce) begin
if (LRUWriteEn) begin
LRUMemory[CAdr] <= NextLRU;
if(InvalidateCache) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
else if (LRUWriteEn) begin
LRUMemory[PAdr] <= NextLRU;
CurrLRU <= #1 NextLRU;
end else begin
CurrLRU <= #1 LRUMemory[CAdr];

4
pipelined/src/cache/cacheway.sv vendored
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@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
input logic SelFlush,
input logic VictimWay,
input logic FlushWay,
input logic Invalidate,
input logic InvalidateCache,
input logic FlushStage,
// input logic [(`XLEN-1)/8:0] ByteMask,
input logic [LINELEN/8-1:0] LineByteMask,
@ -127,7 +127,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
if (reset) ValidBits <= #1 '0;
if(ce) begin
ValidWay <= #1 ValidBits[CAdr];
if(Invalidate & ~FlushStage) ValidBits <= #1 '0;
if(InvalidateCache & ~FlushStage) ValidBits <= #1 '0;
else if (SetValidEN) ValidBits[CAdr] <= #1 1'b1;
else if (ClearValidWay & ~FlushStage) ValidBits[CAdr] <= #1 1'b0;
end