Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Added comment.

Browse Source
This commit is contained in:
Ross Thompson 2022-09-20 09:49:53 -05:00
parent 4c3c517322
commit 822d989383
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
pipelined/src/lsu/lsu.sv
View File

@ -215,6 +215,7 @@ module lsu (
assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
/* verilator lint_on WIDTH */
// *** add ce to bram1... to remove this extra mux control.
dtim dtim(.clk, .reset, .MemRWM,
.Adr(DTIMAdr),