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Removed comment about nonexistent possible bug

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David Harris 2022-11-14 09:52:21 -08:00
parent 84c4558641
commit f9202187ba
1 changed files with 1 additions and 1 deletions
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pipelined/src/mmu/hptw.sv
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@ -224,7 +224,7 @@ module hptw (
if (`XLEN == 32) begin
assign InitialWalkerState = L1_ADR;
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
// *** Possible bug - should be L1_ADR?
// *** Possible bug - should be L1_ADR? If so, applies to 64 bits as well
assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
end else begin
logic GigapageMisaligned, TerapageMisaligned;