Added Quotient/Remainder calcs to normal termination

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -65,12 +65,12 @@ module fdivsqrt(
   logic WZero;
   logic SpecialCaseM;
   logic [`DIVBLEN:0] n, m;
-  logic OTFCSwap, ALTB, BZero;
+  logic OTFCSwap, ALTB, BZero, As;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
     .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, 
-    .n, .m, .OTFCSwap, .ALTB, .BZero,
+    .n, .m, .OTFCSwap, .ALTB, .BZero, .As,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
     .clk, .reset, .FmtE, .XsE, .SqrtE, 
@@ -85,6 +85,6 @@ module fdivsqrt(
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
     .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
-    .MDUE, .n, .ALTB, .m, .BZero,
+    .MDUE, .n, .ALTB, .m, .BZero, .As,
     .QmM, .WZero, .DivSM);
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -38,16 +38,16 @@ module fdivsqrtpostproc(
   input  logic Firstun,
   input  logic SqrtM,
   input  logic SpecialCaseM,
-  input  logic RemOp, MDUE, ALTB, BZero,
+  input  logic RemOp, MDUE, ALTB, BZero, As,
   input  logic [`DIVBLEN:0] n, m,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM
 );
   
-  logic [`DIVb+3:0] W;
+  logic [`DIVb+3:0] W, Sum;
   logic [`DIVb:0] PreQmM;
-  logic NegSticky;
+  logic NegSticky, PostInc;
   logic weq0;
   logic [`DIVb:0] IntQuot, IntRem;
 
@@ -73,9 +73,33 @@ module fdivsqrtpostproc(
   
 
   // Determine if sticky bit is negative
-  assign W = WC + WS;
+  assign Sum = WC + WS;
+  assign W = $signed(Sum) >>> `LOGR;
   assign NegSticky = W[`DIVb+3];
+  assign RemD = {4'b0000, D, {(`DIVb-`DIVN){1'b0}}};
 
+  always_comb 
+    if (~As)
+      if (NegSticky) begin
+        assign IntQuot = FirstUM;
+        assign IntRem  = W + RemD;
+        assign PostInc = 0;
+      end else begin
+        assign IntQuot = FirstU;
+        assign IntRem  = W;
+        assign PostInc = 0;
+      end
+    else 
+      if (NegSticky | weq0) begin
+        assign IntQuot = FirstU;
+        assign IntRem  = W;
+        assign PostInc = 0;
+      end else begin 
+        assign IntQuot = FirstU;
+        assign IntRem  = W - RemD;
+        assign PostInc = 1;
+      end
+  
    // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
 
   assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -42,7 +42,7 @@ module fdivsqrtpreproc (
 	input  logic [2:0] 	Funct3E, Funct3M,
 	input  logic MDUE, W64E,
   output logic [`DIVBLEN:0] n, m,
-  output logic OTFCSwap, ALTB, BZero,
+  output logic OTFCSwap, ALTB, BZero, As,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb+3:0] X,
   output logic [`DIVN-2:0] Dpreproc
@@ -56,7 +56,7 @@ module fdivsqrtpreproc (
   // Intdiv signals
   logic  [`DIVb-1:0] ZeroBufX, ZeroBufY;
   logic  [`XLEN-1:0] PosA, PosB;
-  logic  As, Bs, OTFCSwapTemp;
+  logic  Bs, OTFCSwapTemp;
   logic  [`XLEN-1:0] A64, B64;
   logic  [`DIVBLEN:0] Calcn, Calcm;
   logic  [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;