Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Continued simplifying fdivsqrt postprocessing

Browse Source
This commit is contained in:
David Harris 2022-09-07 07:02:22 -07:00
parent b0ff3a0952
commit c8e0ea067e
2 changed files with 2 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
pipelined/src/fpu/fdivsqrt.sv
View File

@ -70,8 +70,8 @@ module fdivsqrt(
.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
.Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
fdivsqrtfsm fdivsqrtfsm(
.reset, .qn, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN,
.WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.reset, .XsE, .SqrtE,
.Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE,
.XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
fdivsqrtiter fdivsqrtiter(

6
pipelined/src/fpu/fdivsqrtfsm.sv
View File

@ -33,24 +33,18 @@
module fdivsqrtfsm(
input logic clk,
input logic reset,
input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC,
input logic XInfE, YInfE,
input logic XZeroE, YZeroE,
input logic XNaNE, YNaNE,
input logic DivStart,
input logic XsE,
input logic SqrtE,
input logic SqrtM,
input logic StallE,
input logic StallM,
input logic [`DIVN-2:0] D, // U0.N-1
input logic [`DURLEN-1:0] Dur,
input logic [`DIVCOPIES-1:0] qn,
input logic WZero,
output logic [`DURLEN-1:0] EarlyTermShiftE,
// output logic DivSE,
output logic DivDone,
// output logic NegSticky,
output logic DivBusy
);