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1156 Commits

Author SHA1 Message Date
David Harris
2449e06e55 Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported 2024-01-25 21:03:41 -08:00
David Harris
17f579d4ba Reenabled fmadd.h, which is really supported by Zfh 2024-01-24 07:46:50 -08:00
Rose Thompson
117ff1828a
Merge pull request #590 from openhwgroup/revert-589-shiftcorrectiondebug 
Revert "more shiftcorrection bug fixes"
 2024-01-23 16:05:30 -06:00
Rose Thompson
d5bbb5ea27 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-01-23 14:37:11 -06:00
David Harris
4ffa5e7b0a Coverage improvements 2024-01-22 09:49:24 -08:00
David Harris
171430a695 FPU and PMP tests 2024-01-21 14:41:22 -08:00
David Harris
ff055c404c fpu coverage improvements 2024-01-21 13:17:56 -08:00
David Harris
9d4a14b209 coverage improvements 2024-01-21 11:39:51 -08:00
David Harris
d801bf5d6c
Revert "more shiftcorrection bug fixes" 2024-01-21 10:41:14 -08:00
David Harris
9e6fa8076f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-01-21 10:15:38 -08:00
Kevin Kim
1459943a75 more shiftcorrection bug fixes 2024-01-21 10:08:48 -08:00
David Harris
69218b4b86 Coverage improvements 2024-01-21 10:03:07 -08:00
David Harris
17c9be7695 Cleanup typos, remove Zicond from riscof until it is working 2024-01-18 21:36:52 -08:00
David Harris
911b400af2 Fault on misaligned AMO 2024-01-18 13:13:56 -08:00
Rose Thompson
4c2ba2b0b4 Added StoreStall back to csrc. 2024-01-18 14:43:34 -06:00
Rose Thompson
81d006536a Lint passes with 32-bit no D$, but many regressions fail. 2024-01-18 09:48:44 -06:00
David Harris
d5e102d520 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-01-18 07:38:25 -08:00
Rose Thompson
ff6bb3be0c Fixed another bug with virtual memory and no caches. 2024-01-18 09:29:52 -06:00
Rose Thompson
e8474373e4 Fixed it so Virtual Memory work without a D$. 2024-01-18 09:18:17 -06:00
David Harris
74b242ce5c Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow 2024-01-17 12:25:06 -08:00
Rose Thompson
2d3dc55986 Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting. 2024-01-17 12:19:10 -06:00
David Harris
4cfc86140c Zfa fmvh complete and passing tests: 2024-01-17 06:18:00 -08:00
David Harris
07e7e02241 Coded Zfa fmvp but no tests exist 2024-01-16 21:26:42 -08:00
David Harris
8654375f26 Zfa fminm/fmaxm/fltq/fleq implemented and tested 2024-01-16 20:03:54 -08:00
David Harris
9d57002c07 Zfa fli support working for F and D (add fli.sv module) 2024-01-16 17:27:59 -08:00
David Harris
0588d611ea Zfa fli support working for F and D 2024-01-16 17:27:40 -08:00
Rose Thompson
ed0f0d924b
Merge pull request #577 from davidharrishmc/dev 
Zfh fix and typo corrections
 2024-01-16 14:23:23 -06:00
David Harris
846a0c4d50 Check fma operations don't support H precision 2024-01-16 11:12:06 -08:00
David Harris
1a77c08f6e Fixed issues 575 and 477 about FPU tests failing when Zfh = 1. 2024-01-16 10:46:44 -08:00
David Harris
dcd40c6be7 Fixed spelling of output 2024-01-16 10:27:31 -08:00
David Harris
abecc98563 Fixed spelling of precision 2024-01-16 10:26:00 -08:00
Rose Thompson
ff5554ca61 Atomics work correctly without a d cache. 2024-01-16 10:43:20 -06:00
Rose Thompson
dfe5ef4427 Added logic for the non-cache atomics. 2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185 Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit. 2024-01-15 17:36:01 -06:00
Rose Thompson
614a83331f Fixed part of issue #405. 
The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
 2024-01-15 17:29:00 -06:00
Rose Thompson
83df3dfe83 Fixed the zifencei bug (part of issue 405). 2024-01-15 16:02:37 -06:00
David Harris
0235970313 Optimized away unused support for fmv with quads 2024-01-15 13:40:12 -08:00
David Harris
da4eca4854 Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. 2024-01-15 13:24:57 -08:00
David Harris
9e78a7e290 Incorporated jstine fixes of FPU special case and testbench for conversion 2024-01-15 07:25:08 -08:00
David Harris
ed9fa07ba3 tests/coverage/tlbmisc.S 2024-01-15 07:16:11 -08:00
David Harris
fd181169fe Corrected spelling of negative 2024-01-15 07:15:23 -08:00
James E. Stine
b14cd67bef Values for IEEE 754 vs. RISC-V Table 11.4 in the RISC-V Unprivileged ISA 2024-01-14 22:08:42 -06:00
Jordan Carlin
51f670c821
Merge branch 'openhwgroup:main' into main 2024-01-12 19:43:01 -08:00
Rose Thompson
dd5f69cb78
Merge pull request #565 from davidharrishmc/dev 
Dev
 2024-01-12 21:30:27 -06:00
Jordan Carlin
092d10a3cd correct c.sext.b encoding and remove unreachable code in 01100 case 2024-01-12 19:09:10 -08:00
David Harris
d7b016e8f3 Cleaned up Zicond implementation 2024-01-12 18:12:52 -08:00
David Harris
6226c3db96
Revert "Fixes for Issue #541" 2024-01-12 07:50:13 -08:00
James E. Stine
e707eeb7c8 THis includes fix for special case when conversion from fp to int/long. The previous src did not test both the flags and result and so missed this subtle bug when an Invalid happens for this type of conversion. These results are indications of undefined behavior for these operations. All fp operations now passs when this update is fixed. Much of the information why these outputs should occur is somewhat alluded to by Pascal Cuoq originally from INSA in Lyon here: https://frama-c.com/2013/10/09/Overflow-float-integer.html 2024-01-12 00:37:50 -06:00
Rose Thompson
ceae2bc714
Merge pull request #561 from davidharrishmc/dev 
Added Zicond support
 2024-01-11 10:20:01 -06:00
David Harris
9eb6d9c8b8 Added Zicond support 2024-01-11 07:37:15 -08:00
Rose Thompson
a932bf6b66 Removed unnecessary spill for compressed aligned to end of cache line or uncached access. 2024-01-10 13:06:16 -06:00
Rose Thompson
588e1caeba Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries. 2024-01-06 22:29:16 -06:00
David Harris
67124b0c7f Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough 2024-01-06 07:11:25 -08:00
David Harris
0781cd4a44 Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate 2024-01-05 22:45:15 -08:00
Rose Thompson
1f3792c823 Fixed bug # 547, but there are other bugs which follow. 2024-01-05 23:32:10 -06:00
Rose Thompson
edc56c669e Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
David Harris
680a014876 Finished LSU tlbcontrol coverage tests 2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE 2024-01-02 00:35:17 -08:00
David Harris
f4ee05e1ea Coverage improvements 2024-01-01 08:31:09 -08:00
David Harris
e5ac2d5ef0 Modified align fsm to make coverage easier 2024-01-01 08:21:31 -08:00
David Harris
6181639003 Named IFU decomp generate block 2024-01-01 07:37:40 -08:00
David Harris
c52aef86a6 Fixed coverage exclusions that no longer reference code properly 2023-12-31 20:35:08 -08:00
David Harris
8795a9db7a Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-12-31 20:26:47 -08:00
David Harris
536539237c Fixed exclusion tags in pmachecker 2023-12-31 20:20:31 -08:00
Rose Thompson
626b89320c More cleanup. 2023-12-29 16:51:39 -06:00
Rose Thompson
730efefc41 Cleanup. 2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2 Restored cache store delay hazard. 2023-12-29 16:10:27 -06:00
Rose Thompson
0264a17f77 Reverted dtim to use store delay stall, but only (load after store). 2023-12-29 16:06:30 -06:00
Rose Thompson
fbab9f6c6d Updated comments about AMO and CMO stalls. 2023-12-29 15:31:11 -06:00
Rose Thompson
f59fa5089d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-29 15:13:18 -06:00
Rose Thompson
8030b7d100 Added partial code for uncached amo operations. 
Minor fix for Makefile so coverage tests build.
 2023-12-29 15:07:20 -06:00
Rose Thompson
7afeee9807 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-29 14:49:36 -06:00
Jordan Carlin
2fa243c46e fixed coverage exclusions in lsu and ifu 2023-12-29 11:18:23 -08:00
Rose Thompson
52dad4f130 cbo.zero works for uncached memory now! 2023-12-29 11:11:06 -06:00
Rose Thompson
d1456b2471 Progress on fixing cbo.zero for uncached memory regions. 2023-12-29 11:03:38 -06:00
Rose Thompson
482529394a Fixed some of the uncached ifu bugs. 2023-12-29 09:53:22 -06:00
David Harris
2c2f692f3a Moved forwarding logic into controller 2023-12-26 21:17:01 -08:00
David Harris
e8df856fdb Renamed CMOp to CMOpM in mmu and cache 2023-12-25 05:57:41 -08:00
David Harris
6395cd0284 Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match 2023-12-21 12:29:37 -08:00
David Harris
06ddccd983 Fixed typo in IFU 2023-12-20 20:22:17 -08:00
David Harris
8eace30f49 Moved UnalignedPCNextF mux into IFU 2023-12-20 16:18:31 -08:00
David Harris
8552369687 Merged PR538, delete unused tests 2023-12-20 13:30:31 -08:00
Rose Thompson
b68dd74f89 Reverted logic to bit change. 2023-12-20 13:16:32 -06:00
Rose Thompson
18a96740d5 Revert RAM logic to bit change. 
Added logic to hptw to prevent x propagation.
 2023-12-20 13:10:20 -06:00
Rose Thompson
9de434a61b "Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis. 2023-12-20 12:05:25 -06:00
Rose Thompson
9ee1ffe8fe Almost working with modelsim and verilator. 2023-12-20 11:29:31 -06:00
Rose Thompson
d617eb0977 DON'T keep this commit. 2023-12-19 16:56:40 -06:00
David Harris
b0f34a6377 Made priority of misalignment depend on ZICCLSM_SUPPORTED and made StoreAmo take prioirty over load faults 2023-12-19 12:51:45 -08:00
David Harris
6186181d46
Merge pull request #537 from ross144/main 
Almost having working Verilator.  One issue in the testbench remains.
 2023-12-18 18:13:56 -08:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
Rose Thompson
1d36ce3328 Fixed lint issue. 2023-12-18 12:03:54 -06:00
David Harris
6cb4a9e905 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-12-15 19:27:10 -08:00
David Harris
bbdcfe24ca
Merge pull request #533 from ross144/main 
Finally fixed the store delay hazard bug.
 2023-12-15 19:13:53 -08:00
Rose Thompson
438451ee02 Fixed the AMO hazard. 2023-12-15 11:55:54 -06:00
David Harris
51b43bffa3 ALU cleanup 2023-12-14 19:06:39 -08:00
David Harris
29f57958a9 Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match 2023-12-14 15:32:36 -08:00
David Harris
8eea2bdcc0
Merge pull request #531 from ross144/main 
Updated wavefile
 2023-12-14 14:52:31 -08:00
Rose Thompson
1ca9a8be6d I think I solved the AMO/store hazard issue introduced by removing the store delay hazard. 2023-12-14 16:31:02 -06:00
Rose Thompson
53bf68a585
Merge pull request #528 from davidharrishmc/dev 
Svnapot bug fix
 2023-12-13 21:30:47 -08:00
David Harris
166c98b6f6 Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn 2023-12-13 19:43:17 -08:00